1 Lecture 6 BOOLEAN ALGEBRA and GATES Building a 32 bit processor PH 3: B.1-B.5

2 Lets Build a Processor Almost ready to move into chapter 5 and start building a processor First, let’s review Boolean Logic and build the ALU we’ll need (Material from Appendix B) 32 operation result a b ALU

3 Boolean Algebra In Boolean Algebra, all variables are 0 and 1 and there are 3 operators OR is written as + as in A + B, called logical sum. (Sometimes denoted with A U B) AND is written as ∙, as in A ∙ B, (also denoted AB) called the logical product. (Sometimes denoted by A ∩ B) NOT is written as A’. The result of NOT A is 0 if A is 1 and 1 if A is 0.

4 Laws of Boolean Algebra Identity law: A + 0 = A and A ∙ 1 = A Zero and One laws: A + 1 = 1 and A ∙ 0 = 0 Inverse laws: A + A’ = 1 and A ∙ A’ = 0 Commutative laws: A + B = B + A and A ∙ B = B ∙ A Associative laws: A + (B + C) = (A + B) + C A ∙ (B ∙ C) = (A ∙ B) ∙ C Distributive laws: A ∙ (B + C) = A ∙ B + A ∙ C A + (B ∙ C) = (A + B) ∙ (A + C) DeMorgan’s laws: (A + B)’ = A’ ∙ B’ and (A ∙ B)’ = A’ + B’

5 Boolean Algebra & Gates Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true Show the truth table for these three functions. Show the Boolean equations for these three functions. Show an implementation consisting of inverters, AND, and OR gates.

6 Truth Tables

7 Sum of Products The sum of products form is constructed from a truth table by choosing only those inputs that result in an output of 1 and forming the product of the inputs that are 1 and the complements of the inputs that are false. The sum of all such products gives an implementation of the function. For D this would mean D = A’B’C + A’BC’ + A’BC + … (7 terms in all). It works but we can do it easier by noting that D’ = A’B’C’. By one of DeMorgan’s Laws we have D = A + B + C

8 Boolean Equations D = A + B + C F = ABC E = ABC’ + AB’C + A’BC or E = (AB + BC + AC) (ABC)’ It is easy to show the two equations for E are equivalent by using truth tables or by using DeMorgan’s law to change (ABC)’ into A’ + B’ + C’, then using the distributive law a few times.

9 Another example of Sum of Products The sum of products gives D = A’B’C + A’BC’ + AB’C’ + ABC

10 Simplification of Boolean Expressions The Karnaugh map is a graphic method that can handle Boolean expressions up to 6 variables It is a simplification method that uses the following relations: x + x’ = 1 and y ∙ 1 = 1 ∙ y = y Basic idea is the sum of two expressions can be combined and simplified if they have a distance of 1 where distance is defined as follows: The distance between two product terms is equal to the number of literals that occur differently, i.e., one is complemented while the other is not. For example A’B’C and A’B’C’ have a distance of 1 whereas A’BC and A’B’C’ have a distance of 2. Now the sum of the distance 1 pair can be simplified as follows: A’B’C + A’B’C’ = A’B’(C + C’) = A’B’

11 A one-variable Boolean function. (a) Truth table. (b) Karnaugh map.

12 A two-variable Boolean function. (a) Truth table. (b) Karnaugh map

13 An illustrative three-variable Boolean function. (a) Truth table. (b) Karnaugh map.

14 A four-variable Boolean function. (a) Truth table. (b) Karnaugh map.

15 Karnaugh map for a four-variable map functions.

16 Typical map subcubes for the elimination of one variable in a product term.

17 Typical map subcubes for the elimination of two variables in a product term.

18 Typical map subcubes for the elimination of three variables in a product term.

19 Addition

20 Adder

21 You can see that the carry out is correct with a Karnaugh map if it is not obvious already bc a You have a column of two 1’s that gives bc, a left most row of two 1’s that gives ac and a right most row of two 1’s that gives ab

22 Exclusive-Or Truth table xyx xor y (x xor y)’ Equation x xor y = x’y + xy’ Where xy means x and y and x + y means x or y

23 Exclusive-or continued The following equation can be represented as (a xor b) xor carryin Proof: (a xor b) xor ci = (ab’ + a’b) ci’ + (ab’ + a’b)’ ci = (ab’ + a’b) ci’ + (a’b’ + ab) ci. Note it is easily shown that (a xor b)’ = a’b’ + ab

24 Realization of a full binary adder

25 Parallel (Ripple) binary adder

26 A 32-bit Ripple Carry Adder/Subtractor  Remember 2’s complement is just complement all the bits add a 1 in the least significant bit A 0111  0111 B  + 1-bit FA S0S0 c 0 =carry_in c1c1 1-bit FA S1S1 c2c2 S2S2 c3c3 c 32 =carry_out 1-bit FA S 31 c A0A0 A1A1 A2A2 A 31 B0B0 B1B1 B2B2 B 31 add/sub B0B0 control (0=add,1=sub) B 0 if control = 0, !B 0 if control = 1

27 Let's build an ALU to support the and and or instructions –we'll just build a 1 bit ALU, and use 32 of them For AND just use an AND gate and for OR just use an OR gate b a operation result opabres An ALU (arithmetic logic unit)

28 Selects one of the inputs to be the output, based on a control input S causes A or B to be selected. Lets build our ALU using a MUX: S C A B 0 1 Review: The Multiplexor note: we call this a 2-input mux even though it has 3 inputs!

29 Not easy to decide the “best” way to build something –Don't want too many inputs to a single gate –Don’t want to have to go through too many gates –for our purposes, ease of comprehension is important Let's look at a 1-bit ALU for addition: How could we build a 1-bit ALU for add, and, and or? How could we build a 32-bit ALU? Different Implementations c out = a b + a c in + b c in sum = a xor b xor c in

30 Building a 32 bit ALU

31 Two's complement approach: just negate b and add. How do we negate? A very clever solution: What about subtraction (a – b) ?

32 Subtractor circuit from modified adder

33 Binary adder/subtractor

34 Adding a NOR function Can also choose to invert a. How do we get “a NOR b” ? Invert both a and b and input to an and gate since (a + b)’ = a’b’

35 Need to support the set-on-less-than instruction (slt) –remember: slt is an arithmetic instruction –produces a 1 if rs < rt and 0 otherwise –use subtraction: (a - b) < 0 implies a < b Need to support test for equality (beq $t5, $t6, $t7) –use subtraction: (a - b) = 0 implies a = b Tailoring the ALU to the MIPS

Supporting slt Can we figure out the idea? Handling the most significant bit

37 All other bits for slt

38 Supporting slt

39 Equality Test If a – b = 0 in the slt test the two numbers are equal. One can add a test for this by setting an output flag, zero = 1 if the two values are equal and to 0 otherwise. Therefore zero can be defined by Zero = (Result31 + Result30 + … + Result0)’ It can then be added as output as in the following diagram.

40 Equality Notice control lines: 0000 = and 0001 = or 0010 = add 0110 = subtract 0111 = slt 1100 = NOR The right two bits are the operation Note: zero is a 1 when the result is zero!

41 Conclusion We can build an ALU to support the MIPS instruction set –key idea: use multiplexor to select the output we want –we can efficiently perform subtraction using two’s complement –we can replicate a 1-bit ALU to produce a 32-bit ALU Important points about hardware –all of the gates are always working –the speed of a gate is affected by the number of inputs to the gate –the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) Our primary focus: comprehension, however, –Clever changes to organization can improve performance (similar to using better algorithms in software) –We saw this in multiplication, let’s look at addition now

42 Reading material for next time PH 3: B.6-B.11