Introduction First 32 bit Processor in Intel Architecture. Full 32 bit processor family Sixth member of 8086 Family SX

Salient Features With 32 bits able to address 4Gbytes of physical memory. Maximum segment size is 4Gb. 16 k(16384) number of segments. 64 Terabytes of memory(16K * 4Gb) Pages of 4KBytes.

Cont. 3 modes of operation. 1)Real Mode. 2)Protected Mode 3)Virtual 8086 Mode.

Architecture Allow Parallel Processing using six functional units. 1.Execution Unit 2.Segment Unit 3.Page Unit 4.Prefetch Unit 5.Decode Unit 6.Bus Unit.

Bus Interface Unit Interface To Outside Environment. Includes 32 bit Data Bus,32 Address Bus and signals needed to control transfers over the bus. Supports 8-bit,16-bit,32-bit data transfers. Demultiplexed data and address lines. All external Bus operations.

Cont.. Latches and drivers for address bus. Transceivers for the data bus. Control Logic for signaling memory, I/O and interrupt acknowledge bus cycle.

Prefetch Unit Instruction Stream Queue. Prefetch 16 bytes of instruction code. If queue is not full and having size for 4 more opcode bytes and execution don’t want the control of bus then prefetch unit will supply address to bus interface unit to fetch next instruction. Instruction Decoder.

Cont.. 4 bytes of instruction in single memory cycle. Idle states? Also responsible for prioritizes bus activity.

Decode Unit Decode Unit accesses the output of the prefetch unit’s instruction queue. Decode the instructions into microcode instruction format used by EU. Instruction decoding is offloaded from EU. 3 decoded instruction queue.

Microcode Instruction R2 <- R1+R2 0. R1 out, Y in 1. R2 out, Add, Z in 2. Z out, R2 in

Execution Unit Arithmetic and Logic Unit. Registers Special Multiply divide and shift hardware. Control ROM. Having micro code sequences that define the operation performed by each of DX machine-code instructions.

ALU Logical and Arithmetic Operation. Extra hardware for multiply devide and shift rotate operation.

Segment And Paging System. Memory Management And Protection Services. Address Generation. Address Translation. Segment Checking. Offload this responsibility from bus Interface Unit.

Cont.. Segmentation Unit is having dedicated hardware for high speed address calculation. Logical to linear address translation. Protection Checks. In Protected mode the segment unit performs logical to linear address translation and protection checking.

Paging Unit Protected Mode paging model. Translation Look aside buffer. If paging is enabled then linear address produced by segment unit is input to paging unit.

Data Types of 80386DX 1.Bit 2.Bit field- A group of at the most 32 bits. 3.Bit String- A string of contiguous bits of maximum 4 GBytes in length. 4.Signed Byte. 5.Unsigned Byte. 6.Integer Word- Signed 16 bit data 7.Long Integer-32-bit signed data represented in 2’s complement form.

Cont.. 1.Unsigned Long Integer (Unsigned 32 bit data.) 2.Unsigned Integer Word (Unsigned 16 bit data.) 3.Signed Quad Word.-signed 64 bit data. 4.Unsigned Quad Word– an unsigned 64- bit data. 5.Offset-16 or 32 bit displacement.

Cont.. Pointer-This consist of pair of 16-bit selector and 16/32 bit offset. Character-An ascii equivalent to any of the alphanumeric and control characters. Strings—These are the sequences of bytes, words or double words. Minimum 1 byte and maximum 4 GB. BCD-Decimal digits from 0-9 represented by unpacked bytes. Packed BCD– Two packed BCD digits using byte.i.e from 00 to 99.

Pin Configuration CLK2-input pin provides the basic system clock timing. D0-D31-Act as bidirectional Data bus. BE0# to BE3# -The 32- bit data bus supported by and the memory system of can be viewed as a 4- byte wide memory access mechanism. The 4 byte enable lines BE0 to BE3, may be used for enabling these blanks. Using these 4 enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously.

ADS#--The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The does not have any ALE signals and so this signals may be used for latching the address to external latches.

W/R#– The read and write output pins distinguishes write and read cycles from one another D/C#-- The data/control output pins distinguishes between a data transfer cycle from machine control cycle. M/IO# --O/p pin to distinguish between memory and I/o cycle.

LOCK# The LOCK# o/p pin enables the CPU to prevent the other bus masters from gaining the control of system Bus. NA# The Next Address Input Pin if activated allows address pipelining. READY# The ready signal is to indicate the CPU that the previous bus cycle is completed and next bus cycle will starts.

BS16#--Input Pin allows the interfacing of the 16-bit devices with 32 bit wide data bus. HOLD—The bus hold input allows the other bus masters to gain the control of system bus. HLDA—O/P pin which indicates that valid bus hold request has been received.

BUSY#--I/p pin to indicate Co- processor is busy with the alloted task.