Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-1 Chap. 13 Multiprocessors n 13-1 Characteristics of Multiprocessors  Multiprocessors System = MIMD l An interconnection of two or more CPUs with memory and I/O equipment »a single CPU and one or more IOPs is usually not included in a multiprocessor system n Unless the IOP has computational facilities comparable to a CPU  Computation can proceed in parallel in one of two ways l 1) Multiple independent jobs can be made to operate in parallel l 2) A single job can be partitioned into multiple parallel tasks  Classified by the memory Organization l 1) Shared memory or Tightly-coupled system »Local memory + Shared memory n higher degree of interaction between tasks l 2) Distribute memory or Loosely-coupled system »Local memory + message passing scheme (packet or message 전송 ) n most efficient when the interaction between tasks is minimal n 13-2 Interconnection Structure  Multiprocessor System 을 구성하는 Components l 1) Time-shared common bus l 2) Multi-port memory l 3) Crossbar switch l 4) Multistage switching network l 5) Hypercube system CPU, IOP, 그리고 Memory unit 들을 서로 Interconnection 하는 Components

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-2  Time-shared Common Bus l Time-shared single common bus system : Fig »Only one processor can communicate with the memory or another processor at any given time n when one processor is communicating with the memory, all other processors are either busy with internal operations or must be idle waiting for the bus l Dual common bus system : Fig »System bus + Local bus »Shared memory n the memory connected to the common system bus is shared by all processors »System bus controller n Link each local but to a common system bus Tightly coupled system

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-3  Multi-port memory : Fig l multiple paths between processors and memory »Advantage : high transfer rate can be achieved »Disadvantage : expensive memory control logic / large number of cables & connectors  Crossbar Switch : Fig l Memory Module 의 I/O Port 가 하나인 경우에 Crossbar Switch 를 사용해야 함 l Block diagram of crossbar switch : Fig MM CPUs

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-4 cluster Crossbar- Hierarchies cluster Crossbar Node 4 Cluster PU Node CU Network Interface I/O Local Memory 8 8 Crossbar Switch 사용 예제

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-5  Multistage Switching Network l Control the communication between a number of sources and destinations »Tightly coupled system : PU MM »Loosely coupled system : PU PU l Basic components of a multistage switching network : two-input, two-output interchange switch : Fig l 예제 ) 2 Processor ( P1 and P2 ) are connected through switches to 8 memory modules ( ) : Fig l Omega Network : Fig »2 x 2 Interchange switch 를 사용하여 N input x N output network topology 구성

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-6  Hypercube Interconnection : Fig l Loosely coupled system 에서 사용 l Hypercube Architecture 예제 : Intel iPSC ( n = 7, 128 node ) n 13-3 Interprocessor Arbitration : Bus Control  Single Bus System : Address bus, Data bus, Control bus  Multiple Bus System : Memory bus, I/O bus, System bus l System bus : Bus that connects CPUs, IOPs, and Memory in multiprocessor system  Data transfer method over the system bus l Synchronous bus : achieved by driving both units from a common clock source l Asynchronous bus : accompanied by handshaking control signals

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-7  System Bus 예제 : IEEE Standard 796 MultiBus l 86 signal lines : Tab »Bus Arbitration 신호선 : BREQ, BUSY, …  Bus Arbitration Algorithm : Static / Dynamic l Static : priority fixed »Serial arbitration : Fig »Parallel arbitration : Fig l Dynamic : priority flexible »Time slice (fixed length time) »Polling »LRU »FIFO »Rotating daisy-chain * Bus Busy Line 사용 If this line is inactive, no other processor is using the bus

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-8 n 13-4 Interprocessor Communication & Synchronization  Interprocessor Communication l shared memory : tightly coupled system »Accessible to all processors : common memory »Act as a message center similar to a mailbox l no shared memory : loosely coupled system »message passing through I/O channel communication  Interprocessor Synchronization l Enforce the correct sequence of processes and ensure mutually exclusive access to shared writable data l Mutual Exclusion »Protect data from being changed simultaneous by two or more processor l Mutual Exclusion with Semaphore »Critical Session n Once begun, must complete execution before another processor accesses »Semaphore n Indicate whether or not a processor is executing a critical section »Hardware Lock n Processor generated signal to prevent other processors from using system bus

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors 13-9  Semaphore 를 이용한 shared memory 사용 방법 l 1) TSL SEM 명령 실행 (Test and Set while Locked) »Hardware Lock 신호를 발생시키면서 SEM 비트를 검사 »2 memory cycle 필요 n : Test semaphore (semaphore 를 레지스터 R 로 읽어 들인다 ) n : Set semaphore ( 다른 processor 의 shared memory 사용을 금지 ) l 2) R = 0 인 경우 : shared memory is available R = 1 인 경우 : processor can not access shared memory (semaphore originally set) n 13-5 Cache Coherence  Conditions for Incoherence : Fig , 13 l Multiprocessor system with private caches »Write through : P2, P3 Incoherence »Write back : P2, P3, Main memory Incoherence P1 이 X 에 120 을 Write 하는 경우

Computer System Architecture Dept. of Info. Of Computer. Chap. 13 Multiprocessors  Solution to the Cache Coherence Problem l Software 적인 방법 »1) Shared writable data are non-cacheable »2) Writable data exists in one cache : Centralized global table l Hardware 적인 방법 »1) Monitor possible write operation : Snoopy cache controller l 참고 문헌 : »IEEE Computer, 1988, Feb. “Synchronization, coherence, and event ordering in multiprocessors” »IEEE Computer, 1990, June. “A survey of cache coherence schemes for multiprocessors”