Christian J. Schmidt 14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 CBM FEE Summary on CBM Technological Competence Buildup and Front-End ASIC Development Roads, CBM-XYTER Family, RPC Readout

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Test structures for TID measurements Test structures for SEU measurements Test structures for SET measurements, Q crit Ring oscillator for TID / SEU measurements 1.5 x 1.5 mm² 64 pads 28 core pads 36 pads Technology Evaluation, Fundamental Competences GRISU Test ASIC: UMC 0.180µ Process Evaluation on Radiation Hardness Sven Loechner and the GSI ASIC Lab

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Full Spectrum of Irradiation Test Sites ASIC SEU, SET studies with heavy ion GSI irradiation and test facility (X6 cave in coop with bio physics group, 11.4 MeV/u) SET vulnerability mapping at GSI Micro Beam test site mapping with 700nm resolution Total Ionizing Dose (TID) tests at Inst. for Exp. Nucl. Physics, University of Karlsruhe (60keV X-ray, krad/h)  UMC shows very good annealing behaviour, GRISU irradiation up to 2.5 MRad done Sven Loechner and the GSI ASIC Lab

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 RPC FEE and TDC developments (PADI and GET4 ASICs) Holger Flemming and Harald Deppe for the GET4 TDC developments (GSI ASIC Lab) and Mircea Ciobanu for RPC Front-End integration into PADI ASIC (GSI Detector Lab) Beyond FOPI RPC discrete electronics: 4 ch PADI Front-End ASIC for high resolution timing measurements lower power differential impedance matched input High resolution TDC ASIC Get4 for FAIR timing applications CBM RPC targeted system performance:  t < 80ps PADI and Get4 tested together for the first time

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 PADI System Tests Time resolution of electronics challenge at very low threshold Tests of PADI for R3B Neuland at FZD Daniel Bemmerer, Dmitry Yakorev, Daniel Stach, Andreas Wagner FZD-Dresden PADI tested for the first time on differential output RPC (STAR-counter) D. Gonzalez-Diaz Resolution found: 33ps Efficiency: 83% PADI tested with APDs: stable operation (D. Gonzalez-Diaz) 8 PADI at FOPI Beamtime

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Status of the GET4 and FEET TDC Board Focused on the measured results of the GET4 prototype a second iteration of the 4 channel time core will be submitted in November 2009 Different design variations concerning shielding will be investigated The intention is an enhancement of the nonlinearities (DNL & INL) and an improvement of the time resolution Holger Flemming and Harald Deppe GSI GSI

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 CBM-XYTER Family Development Detector operation with purely data driven readout New production this year to correct temperature coefficient for robust, stable operation supply detector prototypes with enough chips n-XYTER, non rad hard AMS 0.35µ CBM-dedicated FEE chip development CBM STS XYTER Low power, low resolution AGH Krakow, R. Szczygiel et al CBM Gas (TRD) -XYTER higher res., adv. signal processing ZiTi Heidelberg, P. Fischer et al Interim work-horse front-end ASIC for detector prototyping In parallel: chip development started in radiation hard UMC 0.180µ final chips to be expected not before within two years TRD front-end test chip INPN Bucharest, M. Petrovici et al

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Data Driven Front-End: Asynchronous Channel Trigger Testpulse Release Slow Shaper, Energy Fast Shaper, trigger and time stamp Discriminator Output to initiate peak detection n-XYTER prototype as employed in current CBM detector developments New production prepared by Hans Kristian Soltveit (PI Heidelberg) Correction of enormous temp. coeff. Elaborate, full corner analysis for robust operation Reduction of cross talk Submission financed and targeted end of November

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Individual signals are digitized Digital signal processing Development of infrastructure elements included

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Prestudy on data transfer building block Serialized data transfer via copper lines using simple p to p Aurora protocol and preemphasis/deemphasis techniques Test chip realized in UMC 0.180µ (ASIC building block) Stoyan Todorov's and Marco Oster's Diploma Thesis, Peter Fischer, ZITI Heidelberg/Mannheim

UMC 0.18µm radiation hardness studies Sven Löchner GSI Darmstadt 14th CBM Collaboration Meeting October 7th, 2009 TRD 8 channel front-end chip in AMS 0.35µ technology just arrived: First test results presented by G. Caragheorgheopol  optional TRD front-end solution with analogue signal processing  integration into TRD-XYTER chip demands process transfer to UMC 0.180

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 First Test-Chip towards Low Power STS-XYTER Readout Chip Time over threshold energy conversion (ToT) 2.3 mW/channel at 500 ENC/30pF (c.f. ~20mW on n-XYTER) 4 to 6 bit resolution 30 channels Chip Overview - Architecture Silicon Strip Detector CSA Switchable FB Const. Current Discharge Discriminator Trim DACs 6-bit Mux Threshold Address Back-End: FPGA Gating Counters PC-Interface Etc. UMC technology for radiation hardness

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 Last weekend´s very first testing results 0.4 to 42 fC (0.1 to 13 MIPs) adjustable discharge slope resolution vs. rate to be evaluated

14th CBM Collaboration Meeting, Split, Oct. 6 – 9, 2009 FEE Session Summary CBM chip development activities are ramping up Fundamental questions are being answered 3 FEE Test Chips are on the table to be evaluated, Successive chips are in the queue Tool boxes are filling up