Penn ESE370 Fall DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 35: November 24, 2014 Inductive Noise

Today Inductive Responses –Show math, but let’s not get bogged down in Calculating L Where do inductances show up Impact of inductance on digital circuits How address –Want to make sure we get to last two Penn ESE370 Fall DeHon 2

Response What happens here? Penn ESE370 Fall DeHon 3

LC Response Penn ESE370 Fall DeHon 4 V2V2

LC Response Penn ESE370 Fall DeHon 5

LC Response Penn ESE370 Fall DeHon 6

LC Response Penn ESE370 Fall DeHon 7

LC Response Penn ESE370 Fall DeHon 8

LC Response Penn ESE370 Fall DeHon 9

LC Response Penn ESE370 Fall DeHon 10

LC Response Penn ESE370 Fall DeHon 11

Response? Penn ESE370 Fall DeHon 12

RLC Response Penn ESE370 Fall DeHon 13 V2V2

RLC Response Penn ESE370 Fall DeHon 14

RLC Response Penn ESE370 Fall DeHon 15

Solving for w Penn ESE370 Fall DeHon 16

RLC Penn ESE370 Fall DeHon 17

RLC Penn ESE370 Fall DeHon 18

RLC For What happens? –Oscillation Asumming R>0, what else happens? –Decay Penn ESE370 Fall DeHon 19

DecayOscillation RLC For Penn ESE370 Fall DeHon 20

RLC Response (R=100) Penn ESE370 Fall DeHon 21

When Oscillate For what R does this particular circuit oscillate? Penn ESE370 Fall DeHon 22

RLC Response Penn ESE370 Fall DeHon 23

Inductance of Wire Penn ESE370 Fall DeHon 24

Inductance: Wire over Ground Plane Inductance per cm with h=3mil, w=5mil? Penn ESE370 Fall DeHon 25

Lwire Penn ESE370 Fall DeHon 26 C and L per unit length

Chip Inductance C wire = 0.16 pF  for the 1mm) C wire = 0.16nF/m Permeability  0 ≈  Si02 =12.6×10 -7 H/m Permitivity  ox =3.5× F/m Penn ESE370 Fall DeHon 27

On Chip C wire = 0.16 pF  for the 1mm) C wire = 0.16nF/m Permeability  0 ≈  Si02 =12.6×10 -7 H/m Permitivity  ox =3.5× F/m  pH (for 1 mm) Penn ESE370 Fall DeHon 28

Comparisons 5mil trace on PCB (preclass 2) Protoboard wires (0.6mm diameter) –About 7nH/cm – On chip wire –0.28nH/mm = 2.8nH/cm Penn ESE370 Fall DeHon 29

Inductors Bond pads Chip leads Long wire runs Cables Penn ESE370 Fall DeHon 30 Src:

Where Arise Penn ESE370 Fall DeHon 31

Signal Path Penn ESE370 Fall DeHon 32

Power Ground Penn ESE370 Fall DeHon 33

Shared Power/Ground Example: 74x04 Penn ESE370 Fall DeHon 34

Estimate R eq, C eq for gates in parallel –R 0 = 25K  –C 0 = 0.01 fF say 10C 0 =0.1fF for typical load 250 gates switching at clock R eq = 100  C eq =25fF Assume L=1nH How long to settle? Oscillate? Penn ESE370 Fall DeHon 35

Power Ground Penn ESE370 Fall DeHon 36

RLC Response Penn ESE370 Fall DeHon 37

Today’s Chips How many gates? Penn ESE370 Fall DeHon 38

Multiple Power/Ground Pins Use many power/ground pins How many pins on a package? Divide switching gates by pins –To get effective load on each pin Penn ESE370 Fall DeHon 39

How Improve Penn ESE370 Fall DeHon 40

How Improve? Collect thoughts Penn ESE370 Fall DeHon 41

Minimize the L Make wires short Use power and ground planes –Think of power plane as a very wide wire Impact on C and L? Penn ESE370 Fall DeHon 42

Flip Chip, Area IO Penn ESE370 Fall DeHon

Add Good C’s Bypass Capacitors – inside the inductances –On board –On package –On chip Penn ESE370 Fall DeHon 44

Bypass Capacitor Example Penn ESE370 Fall DeHon 45

Bypassed Supplies transistor) Penn ESE370 Fall DeHon 46

Bypassed Output Penn ESE370 Fall DeHon 47

Minimize Current Draw More Power/Ground Pins Slower rise/fall times Spread out switching Penn ESE370 Fall DeHon 48

Idea Long wires are inductive –Avoid them –Especially on power supplies Bypass capacitors help Penn ESE370 Fall DeHon 49 DecayOscillation

Admin Tuesday: Project 2 due Wednesday Lecture –Penn says “Wed. 11/26” is logically a Friday Friday 11/28 is Thanksgiving Holiday Penn ESE370 Fall DeHon 50