VHDL Very High Speed Integrated Circuit Hardware Description Language Shiraz University of shiraz spring 2011

Introduction VHDL Texas Instrument intermetrics IBM Under US department of Defense order for High speed ICs Shiraz University of shiraz spring 2011

Introduction  VHDL is a language for  Simulation  Synthesis  Documentation of complex digital systems. Shiraz University of shiraz spring 2011

VHDL Standards  IEEE std  The latest language reference manual  Not much different from 1993  IEEE std  Most tools uses it.  Used in this tutorial  IEEE std  Old standard, almost obsolete. Shiraz University of shiraz spring 2011

VHDL/FPGA Design Flow Shiraz University of shiraz spring 2011

Design Entity  A component or a system to be designed is a VHDL “design entity ”  VHDL divides entities into two parts:  External (interface): how it connects to other components  Internal (architecture): how it behaves and how it is implemented  Behavioral  Structural  Hybrid Shiraz University of shiraz spring 2011

Design Entity Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Example(cont’d) Shiraz University of shiraz spring 2011

Example(cont’d) Shiraz University of shiraz spring 2011

Example(cont’d) Shiraz University of shiraz spring 2011

Example(cont’d) Shiraz University of shiraz spring 2011

VHDL Construct  Entity definition  Architecture definition  Configuration  Process  Subprogram  Package  A VHDL design can be broken into multiple files. Each file contains entity and architecture definitions, or packages. Shiraz University of shiraz spring 2011

Expressions  An expression is a formula that specifies how to compute a value.  Example (D**3) + ((A*B) mod 2)  VHDL operators: Shiraz University of shiraz spring 2011

Defining scalar types  Syntax: Type identifier is range expression {to|downto} expression; Type identifier is ( list_of_items ); Subtype identifier is type_name range expression {to|downto} expression;  Example Type opcode is (nop,load,store,add,subtract,negate,branch,halt); Type system_state is (unknown, idle, busy, ready); Type bit is (‘0’, ‘1’); Type boolean is (false,true); Type std ulogic is (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’); Subtype small_int is integer range –128 to 127; Subtype bit_index is integer range 31 downto 0; Type frequency is range 0 to 1e15 Units hz; khz=1000 hz; mhz=1000 khz; ghz=1000 mhz; End units; Shiraz University of shiraz spring 2011

arrays  An array is an ordered collection of elements of the same type.  Two types of array can be defined  Constrained arrays:  Type word is array (0 to 15) of bit;  Type byte is array (7 downto 0) of bit;  Type ram is array (0 to 16#FFFF#) of byte;  Type int array is array (1 to 100) of integer ;  Unconstrained arrays  Type bit_vector is array (natural range <>) of bit;  Type string is array (positive range <>) of character;  Type std_ulogic_vector is array (natural range <>) of std_ulogic Shiraz University of shiraz spring 2011

Array Elements & slices  Example: Variable B : bit_vector(7 downto 0); Shiraz University of shiraz spring 2011

Array operations  Shift, rotate and concatenate examples Shiraz University of shiraz spring 2011

Simulation Example Shiraz University of shiraz spring 2011

VHDL Statements VHDL has two kinds of statements  Sequential statements: they are executed one after another, like C or Pascal.  Signal and variable assignments, flow control constructs (if, case,while, loop, …), subprogram call, wait  Concurrent statements: all are executed at the same time.  Processes, block statements, component instantiations, generate statements, concurrent assignments and concurrent procedures Shiraz University of shiraz spring 2011

Syntax  Entity : entity entity_name is [ generic (generic_declarations); ] [ port (port_declarations); ] end [entity] [entity_name];  Generic : generic ( [constant_name : type [:=value]] { ; constant_name : type [:=value] } );  Port : port ( [ port_name : port_mode type { ; port_name : port_mode type } ] ); Shiraz University of shiraz spring 2011

Syntax Port Modes:  In : port can only be read  Out : port can only be assigned  Inout : Can be read and assigned a value. The value read is not the assigned value.  Buffer : Similar to out, but can be read Shiraz University of shiraz spring 2011

Syntax  Architecture architecture architecture_name of entity_name is { declarative_item } begin { concurrent_statement } end [architecture_name];  A declarative item can be any of these:  Use clause  Subprogram declaration and body  Type or subtype declaration  Constant declaration  Signal declaration  Component declaration Shiraz University of shiraz spring 2011

Syntax  Process [label:] process [( sensitivity_list )] { process_declarative_item } begin { sequential_statement } end process ;  The sensitivity list is a list of signals read by the process.  The process declarative items can include :  Use clause  Subprogram declaration and body  Variable and constant declaration  Type and subtype declaration Shiraz University of shiraz spring 2011

Signlas  “Signals” carry information among processes and components in an architecture.  Signal declaration syntax signal signal_name : signal_type [:=expression]; signal address : bit_vector(31 downto 0); signal mem_read : bit := ‘0’;  Signal assignment syntax [Label:] signal_name <= value [after time_expression] address <= x”18FE5900” after 20 ns; mem_read <= ‘1’; data_reg <= ”1101_0010”; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Array Attributes Shiraz University of shiraz spring 2011

Wait Statement  Wait causes a process to wait for an event  Syntax wait [on signal_name {,signal_name}]; wait [until boolean_expression]; wait [for time_expression];  Example wait on a,b; wait until clk=‘1’ and clk’event; wait for 100 us; wait; Shiraz University of shiraz spring 2011

Wait Statement Shiraz University of shiraz spring 2011

if Statement  Syntax [label]: if boolean_expression then {sequential_statement} elsif boolean_expression then {sequential_statement} [else {sequential_statement} ] end if [lable]; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Case Statement  Syntax [Label:] case expression is { when choice => {sequential_statement} } end case [label]; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Loop, While & For Statement  Syntax [label:] loop {sequential_statement} end loop [label];  Syntax [label:] while condition loop {sequential_statement} end loop [label];  Syntax [label:] for identifier in discrete_range loop {sequential_statement} end loop [label]; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Next, Exit, Null  Syntax [label:] next [when boolean_expression]; [label:] exit [when boolean_expression]; [label:] null; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Concurrent Signal Assignment  Conditional signal assignment [label:] Signal_name <= { value when boolean_expression else } value [when boolean_expression];  Selected signal assignment [label:] with expression select signal_name <= { value when choices} value when choices; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2011

Subprograms  Procedures  Generalize a statement  Encapsulate a collection of sequential statements that are executed for their effect  Functions  Generalize an expression  Encapsulate a collection of sequential statements thatcompute a result Shiraz University of shiraz spring 2011

Procedures  Syntax procedure identifier [ ( parameter_list ) ] is { declarations } begin { sequential statements } end [procedure]; Shiraz University of shiraz spring 2011

Example 1 Shiraz University of shiraz spring 2011

Example 2 Shiraz University of shiraz spring 2011

Example 3 Shiraz University of shiraz spring 2011

Functions  Syntax [pure|impure] function identifier [ ( parameter_list ) ] return type_name is { declarations } begin { sequential statements } end [function] [identifier]; Shiraz University of shiraz spring 2011

Example Shiraz University of shiraz spring 2012

IEEE Std_Logic  Multivalued logic:  ‘U’ : Uninitialized  ‘X’ : Forcing Unknown  ‘0’ : Forcing Zero  ‘1’ : Forcing One  ‘Z’ : High Impedance  ‘W’ : Weak Unknown  ‘L’ : Weak Zero  ‘H’ : Weak High  ‘-’ : Don’t care  type std_ulogic is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-');  type std_ulogic_vector is array ( natural range <> ) of std_ulogic; Shiraz University of shiraz spring 2012

IEEE Std_Logic  Std_logic Resolution Table Shiraz University of shiraz spring 2012

State Machine  Finite State Machines:  Moore  Mealy Shiraz University of shiraz spring 2012

State Machine Example 1  Moore Shiraz University of shiraz spring 2012

State Machine Example 1  Moore Shiraz University of shiraz spring 2012

State Machine Example 2  Mealy Shiraz University of shiraz spring 2012

State Machine Example 2  Mealy Shiraz University of shiraz spring 2012