ME 4447/6405 Microprocessor Control of Manufacturing Systems and Introduction to Mechatronics Instructor: Professor Charles Ume Serial Communication Interface

Lecture Outline Types of Data Transmission Parallel Communication Serial Communication Applications Serial Communication Formats Serial Communication with the MC9S12C32 Example

Data Transmission Importance Most electronic devices must communicate with other devices to either control them or send data to them Standardization The two communicating devices must “speak the same language” Key Features Compatibility Data Integrity Speed

Parallel Communication Simultaneous 8-bit transmission Bits must stay synchronized Restricted distance to avoid synchronization problems Theoretically faster (limited by skew) Hardware easier to implement Transmitter Receiver 2nd word 1st word Before the development of high-speed serial technologies, the choice of parallel links over serial links was driven by these factors: Speed: Superficially, the speed of a parallel data link is equal to the number of bits sent at one time times the bit rate of each individual path; doubling the number of bits sent at once doubles the data rate (see Parallel transmission). In practice, skew reduces the speed of every link to the slowest of all of the links. Cable length: Crosstalk creates interference between the parallel lines, and the effect worsens with the length of the communication link. This places an upper limit on the length of a parallel data connection that is usually shorter than a serial connection. Complexity: Parallel data links are easily implemented in hardware, making them a logical choice. Creating a parallel port in a computer system is relatively simple, requiring only a latch to copy data onto a data bus. In contrast, most serial communication must first be converted back into parallel form by a Universal asynchronous receiver transmitter before they may be directly connected to a data bus. The decreasing cost of integrated circuits, combined with greater consumer demand for speed and cable length, has led to parallel communication links becoming deprecated in favor of serial links; for example, IEEE 1284 printer ports vs. USB, Advanced Technology Attachment vs. Serial ATA, SCSI vs. FireWire.

Serial Communication Transfers one bit at a time Requires only one data line Slow compared to parallel transmission Less expensive Transmitter Receiver 2nd word 1st word

Serial vs. Parallel Clock differences between channels No crosstalk between transmission lines Serial communication requires less transfer lines

Applications ATA interface for storage devises (IDE), cable lengths of up to 18” 133 Mbits/sec with 16 bit lines. Serial ATA 1.5Gbits/sec FireWire 8000 Mbits/sec USB 480 Mbits/sec

Synchronization Synchronous Asynchronous Data rates determined by clock rates Continuous transmission to maintain clock synchronization. Faster Asynchronous Transmission can occur at any time Receiver is always listening No idle characters Data words not locked into system timing Requires start and stop bits

Asynchronous Serial Transmission Transmitter and receiver operate independently - Same baud rate - Same data format Requires a start and stop bit to identify each byte of data

Asynchronous Transmission Format Bit Types Start Bit Data Bits Parity Bit Stop Bit Bit types are used to differentiate between words For MC9S12, 10 or 11 bits

Asynchronous Serial Transmission Start Bit If line is idle, it continuously sends high (1) logic bit Each word preceded by start bit Signals receiver that data is about to be transmitted Low (0) logic bit Previously HIGH Start Bit Now LOW

Asynchronous Serial Transmission Stop Bit Stop bit indicates all data has been transmitted 1 or 2 Stop bits (the MC9S12 uses 1 stop bit) Stop Bit 1 Stop Bit 2 Parity or Bit 7

Asynchronous Serial Transmission Data Bits The content of the package Usually 8 bits LSB sent First Ex: This transmitted word is 10111001, or $B9 LSB MSB Data Bit 0 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 7 Data Bit 1 Data Bit 2 Data Bit 6

Parity Bit Used to check that all of the set bits were received Odd parity: bit is set to 1 or 0 to make the sum of all bits odd. Even parity: makes the sum of all bits even. Transmitted Sum = 4 Start 0 1 1 1 0 1 0 0 Parity Stop Received Sum = 3 Start 0 1 1 0 0 1 0 0 Parity Stop Parity bit sent (1) = Parity of signal received (0)

Asynchronous Serial Transmission Parity Bit Used to check for errors Helps verify signal integrity 2 Types: -Even: makes sum of all high bits INCLUDING parity bit EVEN -Odd: makes sum of all high bits INCLUDING parity bit ODD Can be implemented in hardware by MC9S12C32 Parity Bit (H or L) Data Bit 7

An example of even parity start stop 0x52 ? Start Bit Data Bit 0 Data Bit 1 Data Bit 2 Data Bit 3 Data Bit 4 Data Bit 5 Data Bit 6 Data Bit 7 Parity Bit Stop Bit Stop Bit 1 1 1 1 1 1

Transfer Rates Baud Rate: number of individual states that are transmitted per second. Data Rate (bps) Max Distance (ft) 19200 45 9600 76 4800 152 2400 304 1200 608 600 1216 8 bits of data Start bit + Stop bit_____ 10 bit word

Transmission Rates Example Consider baud rate: 4800 baud 12 bits/word = 1 start bit + 8 data bits + 1 parity bit + 2 stop bits Bit rate = (baud rate)*(8 data bits)/(12 bits total) = 3200 bits/s

Signal Standard Serial devices convert TTL/CMOS-level signals to higher voltage bipolar signals state 1: -3V to -25V state 0: 3V to 25V Bit Period Transition Time <125 µs 5 µs 25 ms – 125 µs 4 % of bit period >25 ms < 1ms

Asynchronous Serial Transmission One Data Word Four parts per packet Parity Bit Data Bit 1 Data Bit 3 Data Bit 6 HIGH Stop Bit LOW Start Bit Data Bit 0 Data Bit 2 Data Bit 4 Data Bit 5 Data Bit 7

Start bit - Ideal Case (1) logic-zero sample is preceded by three logic-one samples : start-bit qualifiers (2) start-verification samples (3) data samples

Noise (i) Since verification samples RT3 and RT5 are both high, the RT clock count is reset

Noise (ii) Since verification sample RT3 is high, the noise flag is set Data is correctly sampled by RT8-10

Noise (iii) Since verification sample RT5 is high, the noise flag is set Data is correctly sampled by RT8-10

Noise (iv) Since verification samples RT5 and RT7 are both high, no start bit is found

Serial Communication using the MC9S12C32 Contains receiving and transmitting systems Includes flags to indicate status of system

SCIBDH and SCIBDL $00C8-9 SBR[12:0]: Used to determine baud rate for SCI module. Possible values range from 1-8191 SCI Baud Rate = Bus Clock/(16*SCIBR)

SCICR1 $00CA LOOPS: TXD connected to receiver (1) or normal operation (0) SCISWAI: SCI enabled (0) or disabled (1) in wait mode RSRC: In loop mode, receiver connected to transmitter output internally (0) or externally (1) M: One start bit, eight data bits, one stop bit (0) or One start bit, nine data bits, one stop bit WAKE: Idle line (0) or address mark (1) wakeup ILT: Idle character bit count begins after start (0) or stop (1) bit PE: Parity disabled (0) or enabled (1) PT: Parity type - even (0) or odd (1)

SCICR2 $00CB TIE: Transmit data register empty interrupt disabled (0) or enabled (1) TCIE: Transmit complete interrupt disabled (0) or enabled (1) RIE: Receiver full or receiver overrun interrupt disabled (0) or enabled (1) ILIE: Idle line interrupt disabled (0) or enabled (1) TE: Transmitter disabled (0) or enabled (1) RE: Receiver disabled (0) or enabled (1) RWU: Normal operation (0) or receiver wakeup enabled (1) SBK: No break characters sent (0) or break characters sent (1). Toggling this bit sends one break character out the transmit line

SCISR1 $00CC TDRE: Transmit data register contains data (0) or is empty (1). Flag cleared by reading SCISR1 with TDRE set and then writing to SCIDRL TC: Transmit in progress (0) or complete (1) RDRF: Data not available (0) or available (1) in SCIDR. Flag cleared by reading SCISR1 with TC set and then reading SCIDRL IDLE: Receiver line not idle (0) or idle (1) OR: No overrun (0) or data was received before previous data in SCIDR was read (1) NF: No noise (0) or noise (1) FE: No framing error (0) or framing error (1) PF: No parity error (0) or parity error (1)

SCISR2 $00CD BK13: Break character is 10 or 11 bits (0) or 13 or 14 bits (1) long TXDIR: TXD is used as an input (0) or output (1) in Single Wire Mode (0) RAF: No reception in progress (0) or reception in progress (1)

SCIDRH and SCIDRL $00CE-F Contains received data (when reading) or data to be transmitted (when writing) Note: When accessing using 8-bit instructions, SCIDRH should be written to before SCIDRL is written

Example: Configuring SCI Write a program that receives data and responds with the 2’s complement of the received data. Baud Rate: 9600 Clock rate = 8e6 Hz  baud rate = clock rate/(16*BR) BR = clock rate/(16*baud rate) = 8e6/(16*9600) ≈ 52 Parity: Odd Data bits: 8, 1 parity bit, so we need to use the 9 bit format

Example: Configuring SCI SCIBDH = #$00, SCIBDL = #$34 (52 in decimal) SCICR1 = #$13 - M=1, odd parity enabled Note: parity bit will be determined by hardware SCICR2 = #$0C - Receiver and transmitter enabled

SCIBDH EQU $00C8 SCIBDL EQU $00C9 SCICR1 EQU $00CA SCICR2 EQU $00CB SCISR1 EQU $00CC SCIDRL EQU $00CF ORG $1000 LDAA #$34 STAA SCIBDL ;Set baud rate LDAA #$13 STAA SCICR1 ;Set data format LDAA #$0C STAA SCICR2 ;Enable transmitter and receiver WAIT BRCLR SCISR1,#$20,WAIT ;Check RDRF Flag LDAA SCIDRL ;Get data from SCI data register NEGA ;Perform 2’s complement STAA SCIDRL ;Store result to SCI data reg. BRA WAIT

Questions???