Deterministic Approaches to Analog Performance Space Exploration (PSE) D. Mueller, G. Stehr, H. Graeb, U. Schlichtmann Institute of Electronic Design Automation, TU Muenchen, Munich, Germany

3 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

4 Motivation Analog circuits in mixed-signal systems: –Signal conversion, clock generation, data acquisition,... Performance Space Exploration (PSE): –For given topology and technology of an analog circuit block determine its performance capabilities. –Applications: Visualize Trade-Offs between competing performances Compare topologies which implement same analog functionality Topology selection Bottom-up propagation of information about implementation capabilities in a hierarchical sizing process

5 Methods Extensive search: –Parameter sweep: p (CMOS: W,L) –Performances f obtained by simulation –(high computational costs) Feasible performance space F OpAmp

6 Methods Extensive search: –Parameter sweep: p (CMOS: W,L) –Performances f obtained by simulation –(high computational costs) –Two deterministic approaches DISC/POLY ( see Paper for state-of-the-art ) –What determines the Feasible Performance Space of a circuit block? Sizing constraints Feasible Performance Space F More efficient determination? OpAmp

7 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

8 Sizing Constraints: Formalized design knowledge Basic functional blocks: e. g. current mirror geometrical electrical function robustness i1i1 i2i2 i 2 = K i 1

9 Sizing Constraints: Formalized design knowledge Basic functional blocks: e. g. current mirror geometrical electrical function robustness c(p) ≥ 0 Sizing constraints Reduced Parameter set p Saturation Robustness against local threshold voltage variations (mismatch) i1i1 i2i2 i 2 = K i 1 Analog minimum feature size Reduce effect of channel length modulation

10 Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp VDD VSS Out INnInp Ibias VSS VDD INp INn Ibias Out

11 Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. Current Mir. Load Current Mirror Level Shifter Differential Pair VDD VSS Out INnInp Ibias VSS VDD INp INn Ibias Out

12 Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. Current Mir. Load Current Mirror Level Shifter 4-T Current Mir. Current Mir. Bank Level Shifter Bank Cascode Cur. Mir. Differential Pair VDD VSS Out INnInp Ibias VSS VDD INp INn Ibias Out

13 Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. Current Mir. Load Current Mirror Level Shifter 4-T Current Mir. Current Mir. Bank Level Shifter Bank Cascode Cur. Mir. Differential Pair Differential Stage Cas. Cur. Mir. Bank VDD VSS Out INnInp Ibias VSS VDD INp INn Ibias Out

14 Automatic Constraint Setup Folded–Cascode OpAmp Miller OpAmp Voltage Ref. Current Mir. Load Current Mirror Level Shifter 4-T Current Mir. Current Mir. Bank Level Shifter Bank Cascode Cur. Mir. Differential Pair Differential Stage Cas. Cur. Mir. Bank VDD VSS Out INnInp Ibias VSS VDD INp INn Ibias Out 8 Design Parameters p 62 Sizing Constraints c(p) ≥ 0 11 Design Parameters p 181 Sizing Constraints c(p) ≥ 0

15 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

16 PSE by discretized Pareto Fronts – DISC Feasible Performance Space Pareto Optimal Front for max f 1, max f 2 Utopia point

17 Normal Boundary Intersection – DISC 1.Individual performance optima

18 Normal Boundary Intersection – DISC 1.Individual performance optima 2. Convex hull, discretized

19 Normal Boundary Intersection – DISC 1.Individual performance optima 2. Convex hull, discretized 3. Line search perpendicular to convex hull

20 Topology selection with DISC Folded–Cascode OpAmp Miller OpAmp DC Gain > 75dB Phase Margin > 60 o DC Gain > 75dB Phase Margin > 80 o Folded–Cascode OpAmp Miller OpAmp Folded–Cascode OpAmp

21 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

22 PSE by Polytopal Approximation - POLY Nonlinear problem c(p) ≥ 0 P Simulation f = f(p)f = f(p) F k(f) ≥ 0k(f) ≥ 0 

23 PSE by Polytopal Approximation - POLY Polytope Nonlinear problem Linear description c(p) ≥ 0 P Simulation f = f(p)f = f(p) F k(f) ≥ 0k(f) ≥ 0 P F C Δp ≥ c 0 K Δf ≥ k 0 Δf = F ΔpΔf = F Δp Linearisation at p 0 : Δp = p – p 0  Polytope Linear Circuit Model

24 Results POLY DC Gain > 75dB Phase Margin > 60 o Folded–Cascode OpAmp Miller OpAmp

25 Comparison POLY-DISC Miller OpAmp Folded–Cascode OpAmp DC Gain > 75dB Phase Margin > 60 o

26 Comparison POLY-DISC Miller OpAmp Folded–Cascode OpAmp DC Gain > 75dB Phase Margin > 60 o Points of Linearisation

27 Comparison POLY-DISC Miller OpAmp Folded–Cascode OpAmp DC Gain > 75dB Phase Margin > 60 o Points of Linearisation DISCPOLY 18 min 25 sec3 sec 55 min 38 sec1 min 45 sec Computational time on cluster of 15 Pentium IV ACCURATE FAST

28 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

29 Flat Sizing Process System performances (f c, G c, Q) Circuit parameters (w MN1,l MN1,…) Circuit sizing System specification CIRCUIT LEVEL

30 Hierarchical Sizing Process System performances (f c, G c, Q) System parameters (g m(OTA8), C T(OTA8),…) Circuit performances (g m,φ(f c ),…) Circuit parameters (w MN1,l MN1,…) System specification System sizing Circuit sizing SYSTEM LEVEL CIRCUIT LEVEL = Circuit specification ↓

31 Hierarchical Sizing Process System specification System sizing Circuit sizing SYSTEM LEVEL CIRCUIT LEVEL Circuit specification Performance Space Exploration Feasible system parameters System level constraints ↑ ↓ WE NEED Too ambitious system sizing Unrealistic circuit specifications ↓ Circuit sizing can not meet specification TO AVOID Resizing Loop

32 Hierarchical Sizing of OTA-C Filter Sizing without system constraints Sizing with system constraints Filter Spec. f c = 2 MHz; G c ≥ 20 dB; Q ≥ 15 SYSTEM LEVEL CIRCUIT LEVEL

33 OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF Hierarchical Sizing of OTA-C Filter f c [MHz]G c [dB]Q Sizing without system constraints Sizing with system constraints OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF f c [MHz]G c [dB]Q OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF Filter Spec. f c = 2 MHz; G c ≥ 20 dB; Q ≥ 15 OTA 5 Spec. g m = μS C in = 32.9 fF φ(f c ) = deg R out = MΩ C out = 21.6 fF OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF OTA 5 Spec. g m = μS C in = fF φ(f c ) = deg R out = MΩ C out = 22.9 fF System level sizing SYSTEM LEVEL CIRCUIT LEVEL

34 OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF Hierarchical Sizing of OTA-C Filter f c [MHz]G c [dB]Q g m [μS ] C in [fF] φ(f c ) [deg] R out [MΩ] C out [fF] f c [MHz]G c [dB]Q Sizing without system constraints Sizing with system constraints OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF f c [MHz]G c [dB]Q f c [MHz]G c [dB]Q g m [μS ] C in [fF] φ(f c ) [deg] R out [MΩ] C out [fF] OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF Filter Spec. f c = 2 MHz; G c ≥ 20 dB; Q ≥ 15 OTA 5 Spec. g m = μS C in = 32.9 fF φ(f c ) = deg R out = MΩ C out = 21.6 fF OTA 5 spec. gm = μS Cin = 32.9 fF φ(fc) = deg Rout = MΩ Cout = 21.6 fF OTA 5 Spec. g m = μS C in = fF φ(f c ) = deg R out = MΩ C out = 22.9 fF System level sizing Circuit level sizing SYSTEM LEVEL CIRCUIT LEVEL

35 Outline Introduction to Performance Space Exploration (PSE) Sizing constraints and structural circuit analysis PSE by discretized Pareto Optimal Fronts (DISC) PSE by Polytopal Approximations (POLY) Application to hierarchical sizing Conclusions

36 Conclusions Support designer in comparing different topologies for implementing a given analog functionality Provide information about underlying implementations on system level avoiding resizing loops Deterministic Performance Space Exploration Approaches based on sizing constraints POLY DISC ACCURATE FAST