doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 1 Proposal for extension of the IEEE b PHY to Higher Rates (>20 Mbps) V.S. Somayazulu, S. Kandala, J.M. Kowalski, C.K. Park Sharp Laboratories of America, Inc.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 2 Introduction b Extends DSSS to 5.5 and 11 Mbps, while maintaining some backwards compatibility. Purpose of the Study Group is to extend to rates higher than 20 Mbps with the same level of compatibility. i.e., maintain the same chip rate and continue to employ the same CCK codes
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 3 Introduction employed for 5.5 and 11 Mbps rates of b. Ensures that the receiver design is mostly unchanged.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 4 Proposal (1) CCK codes currently used are 8 chips long. Same symbol rate and codeword length for higher rates through bandwidth efficient multi-level modulation. M-PSK in this case. Same structure for the CCK codes. To achieve 22 Mbps, we need 16 bits/codeword.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 5 Proposal (2) To encode these 16 bits with the four phase parameters 1, 2, 3, 4, each of the phase parameters must encode 4 bits, and thus each needs to be a 16-PSK symbol. The mapping that we propose is very close to the existing mapping. 1 is differentially encoded using the four bits d 0 to d 3 as shown in Table 1.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 6 Proposal (3)
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 7 Proposal (4)
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 8 Proposal (5) For each of the remaining phases 2, 3, and 4, we obtain the mapping from successive groups of 4 input bits d 4 … d 7, d 8 … d 11, and d 12 … d 15 respectively, as shown in Table 2. The minimum Euclidean distance, normalized for the same E b, is 1.56.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 9 Proposal (6) Results in higher E b /N 0 requirement to meet the same PER.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 10 Fast Transform Receiver : Method 1 The received signal vector is pre-weighted with a vector formed by the 64 combinations of the triple ( 2, 3, 4 ) and presented to the same butterfly hardware as in the 5.5/11 Mbps and the largest result for each presentation is stored.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 11 Fast Transform Receiver : Method 1 The largest among this set of “local” maxima is selected, and the data bits are decoded from the associated i and i values for that maximum correlation result.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 12 Fast Transform Receiver : Method 2 The butterfly/fast transform hardware is changed so that each stage of the butterfly has an additional “twiddle factor” exp(j i ) (multiplying the existing +/- 1, +/- j twiddle factor).
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 13 2 Chip Butterfly ( 2 ) 4 Chip Butterfly ( 3 ) 8 Chip Butterfly ( 4 ) 8 Input Samples 2 3 4 Select the Largest Correlation Value. Decode bits. Fast Transform Structure of Method 2, Using Modified Buttefly
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 14 Sample 1 Sample 2 1 e jj 1 je jj 1 -e jj 1 -je jj Modified 2-Chip butterfly.
doc.: IEEE /069 Submission May 2000 V. S. Somayazulu et. al., Sharp LaboratoriesSlide 15 Conclusions A simple extension of b can be made to accommodate high rates, through the use of bandwidth efficient higher level modulation. Receiver structures are preserved with only minor changes needed to accommodate 16 level as opposed to 4 level decision making.