Reporting of Standard Cell Placement Results Patrick H. Madden SUNY Binghamton CSD BLAC CAD Group

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Presentation transcript:

Reporting of Standard Cell Placement Results Patrick H. Madden SUNY Binghamton CSD BLAC CAD Group

Thanks Prof. Nael Abu-Ghazaleh, Patrika Agarwal, Dr. Charles Alpert, Andrew E. Caldwell, Prof. Jason Cong, Prof. Shananu Dutt, Dr. Hans Eisenmann, Bill Halpin, Dr. Dennis J.-H. Huang, Prof. Andrew B. Kahng, Prof. George Karypis, Faris Khundakjie, Prof. Cheng-Kok Koh, Prof. John Lillis, Igor L. Markov, Antonis Papadimitriou, Prof. Massoud Pedram, Dr. Bernhard Reis, Prof. Majid Sarrafzadeh, Prof. Carl Sechen, Ryon Smey, Dr. Bill Swartz, Arvind Vidyarthi, Dr Dongmin Xu, Xiaojian Yang, and Mehmet Can YILDIZ

Outline l Problem and Motivation l The Benchmarks l Common Metrics l Reported Results l Summary and Future Work

Standard Cells

Standard Cell Design

Objective l Place cells into rows to minimize wire length, congestion, delay, power, area, ….

MCNC Benchmarks l 10+ years old l Up to cells l Golem3 benchmark (IBM) has nearly 100K cells

Half Perimeter Wire Length

Motivation: > 79.9 Yes, that’s correct. Reported results differ widely, and it’s difficult to make comparisons

The Devil is in the Details l How do you measure X? –We do it the same way as everyone else l Well, how exactly is that? –[generally 3 or 4 different responses]

Half Perimeter Wire Length First port defined

Half Perimeter Wire Length Center of cell

Half Perimeter Wire Length Bounding box of pins

Half Perimeter Wire Length Nearest port

Row Spacing

Removal of channel area reduces wire length

Number of Rows Suppose we have an 8x8 mesh…. Primary2: 29[15], 36[14], 28[19][5][7][11][24], 32[8]

Pad Positions

Scaling of Dimensions l Fract, Struct, Biomed, have dimensions scaled by a factor of 2 in TimberWolf based formats l Golem3 has dimensions scaled by a factor of 4

Tool Versions l TimberWolf has many academic and commercial versions l The academic version normally bundled with LAGER does not have the best performance l LAGER generates TW input configured for speed, and not quality

Reported Results: Avqlarge ToolHPWLSpacingPort Location FD98[5]5.38RowOrigin ARP[7]6.54 Dragon[21]5.25RowCenter SPADE[24]6.16NoneCenter Mongrel[11]4.87NoneCenter Feng Shui[23]6.301RowCenter iTools[12]4.78RoutedFirst

> 79.9? Also, center-to-center, vs. first port, different numbers of rows, pad positions Scale by 1/4

Summary l There are many unintentional skewed comparisons l No clear winner, for even a metric as simple as HPWL l If we want better placement tools, we should figure out what better means

Nobody cares about HPWL! l Real objective is to minimize delay, power, area, and make sure the chip can be routed (congestion) l 30% difference in length estimate gives a 51% difference in RC delay for the wire…. l But we have to crawl before we walk

Future Work l Some sort of agreement on HPWL and other metrics l New benchmarks for timing, power, routability (and placement competitions?) l Routing – the trouble in placement pales in comparison…

Suggestions l Zero row spacing l Row numbers to allow square core area l Pads at fixed locations l HPWL to use exact pin locations, minimum area bounding box to contain at least one port from each pin l Make placement results available (and tools too, if possible!)

What’s the Best Placer? l Mine, of course… l But seriously, I have no idea (and would be hard pressed to find a pair of tools where I’m confident that one is superior to the other)

How Good are Industry Tools l So good that no one wants to report results for the MCNC benchmarks l Academic tools don’t really consider congestion, delay, power, …. But how far off are we? How much WL do we lose, or should we expect to lose?