Texas A&M University Department of Computer Science CPSC 321 Computer Architecture Introduction to Course and Five Components of a Computer Instructor Michael E. Thomadakis

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Course Overview ° CPSC 321 – Computer Architecture Course Information -The Crew -Objectives -Scope -Type Material Assignment Types Reporting Work ° Intro to Computer Architecture ° Organization and Anatomy of a Computer

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu CPSC 321 –— Course Information – The Crew ° Instructor: Who:Dr. Michael E. Thomadakis Room:315B HRBB; tel: OH:Friday: 12:30–14:30 or at other times by appointment. ° TAs / GANT 1) Praveen Bhojwani; ; -HRBB 514B; ; -TBA or by appointment. 2) Di - Wu; ; -HRBB 522; ; -TBA or by appointment. 3) Subrata Acharya; ; ° Contact as regularly to obtain your scores. ° Contact as early in case you have questions on assignments or the material.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu ° Homework will be included with laboratory assignments HW is done together by all people doing lab. ° Labs (8 – 10) 1 or 2 persons to do the lab work (number will be explicitly stated), preparation for projects and hands-on for class material, print from web page for current week, complete during lab period, obtain TA check-off same day for grade, if can ’ t finish, due start of next lab. CPSC 321 –— Course Information – Assignment Structure – I

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu ° Projects Major assignments, typically to 2+ weeks to complete in number. ° Teams? each assignment will clearly state if you can work with partner(s) or individually, partners turn in one set of deliverables (reports, files, code, etc.) with both names; receive grade commensurate with their fair contribution to the project, intent: enhanced learning experience, NOT an opportunity to let partner do all the work (why not? Exams and peer evaluation) CPSC 321 –— Course Information – Assignment Structure – II

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Course Requirements ° 100 course points awarded for: examinations, labs, projects, homework, as follows: ItemPercentage Two Midterm Exams30% Final Exam25% Projects30% Labs15% Homework05% ° Labs: Groups of two people (max). ° Projects:Groups of four people (max). ° Homework:Part of labs.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Cheating - Plagiarism ° What is cheating? Studying together in groups is encouraged BUT, submitted work must be your own Common examples of cheating: -find homework solution on Web; -ask to borrow solution “just to take a look”; -copy solution from classmate and modify so it looks different. It is very easy to spot copied work. ° Penalty? We have to report incident to Computer Science Department Head, as per TAMU regulations: Department head’s action includes: -F in course, -suspension, or -expulsion are possible outcomes

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Excused Absence and Make-ups ° Excused Absences : defined by the University; consult the Student's Handbook. ° Usually a condition that objectively impacts the capacity of the student to perform assignments. such as, a DOCUMENTED medical reason. ° Can’t make a midterm, or final? Tell me ahead of time and we will schedule alternate time before exam ° “Forgot to turn in homework / Dog ate computer, etc.” Late assignments are not accepted after the deadline. ° NO LATE LAB, Projects accepted unless a University sanctioned excuse is provided. Proper documentation must be furnished.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Textbooks and Other Material ° Course material: See course homepage and newsgroup OR AND news:tamu.classes.cpsc321 ° Main Text: [PaHe1998] Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, Second Edition, Morgan Kaufmann Publishers, Inc., 1998, ISBN Get 2 nd Edition (  50% text changed; try to get  3rd printing) ° Verilog Hardware Description Language (HDL) and Digital Design: [MMM2002] M. Morris Mano, Digital Design, 3 rd Edition, Prentice Hall, Upper-Saddle River, [BroVra2003] Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, McGraw-Hill, ° Other Notes, Transparencies, as appropriate.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu CPSC321: Course Content Focus Computer Architecture and Engineering Instruction Set DesignComputer Organization InterfacesHardware Components Compiler/System ViewLogic Designer’s View ­ “Building Architect”­ “Construction Engineer”

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Course Organization ° Design Intensive Class to 150 hours per semester per student MIPS Instruction Set ---> “Standard-Cell” (partial) implementation ° HDL System (Verilog): Specification and Simulation Design Description Computer-based "breadboard" Behavior over time Before construction ° Lectures (tentative breakdown): Review 2 ½ weeks on Intro, ISA, MIPS, C  MIPS translation; 2 weeks on technology, HDL, and computer arithmetic (int, FP); 3 weeks on standard Proc. Design and pipelining 1 weeks on advanced pipelining and modern superscalar design 1 weeks on memory and caches 1 1/2 weeks on Memory and I/O ?? Special lectures (parallel processing, supercomputing?)

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu CPSC321: So what's in it for me? (1 / 2) ° In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary. discussion of fast/slow operations and why they are easy/hard to implement in hardware “out of order execution,” branch-prediction and other techniques to increase the average execution rate of instructions ° Experience with the design process in the context of a large complex (hardware) design. Functional Spec  Control & Datapath  “Physical” implementation Modern CAD tools (later on ?) ° Designer's "Conceptual" toolbox.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu CPSC 321: So what's in it for me? (2 / 2) ° Teach Computer Architecture from a software developer’s point of view What the programmer specifies, how it is translated to machine language (ML), how the machine interprets the ML code. Performance impact of s/w and h/w designs; what makes programs run slowly, what h/w features can speed up the execution of programs. ° Learn perenial ideas in computer science and engineering Principle of abstraction, used to study and build complex systems as layers Use Hardware Description Languages ( Verilog ) to design and study correctness and performance of hardware blocks at various detail levels; -Structural vs. Behavioral Specification Stored program concept: instructions and data stored in memory Raw data (binary bit patterns) “mean” different things (integers, floating point numbers, chars, etc.); program determines what the meaning is. Principle of Locality, exploited in a memory hierarchy Greater performance by exploiting instruction parallelism (pipelining) Compilation vs. interpretation to move down the layers of the computer system Principles/Pitfalls of Performance Measurement

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Topics ° Intro to Performance Evaluation Techniques (Measurement) ° Instruction Set Architecture: specification vs. implementation. ° Translation process (e.g., Compilation, Assembly) ° Levels of Interpretation (e.g., Microprogramming) ° Memory Hierarchy (e.g., registers, cache, mem, disk, tape) ° Pipelining and Parallelism (ILP) ° Static vs. Dynamic Scheduling of Instructions (partial coverage) ° Indirection and Address Translation ° Synchronous and Asynchronous Control Transfer ° Timing, Clocking, and Latching ° CAD Programs, Hardware Description Languages, Simulation ° Physical Building Blocks (e.g., CLA, CSA) ° Understanding Technology Trends

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu What is really “Computer Architecture” ° Computer Architecture = Instruction Set Architecture (ISA) + Machine Organization (MO) + ° ISA ≡ Definition of What the Machine Does, -Logical View; -What the executable perceives as the capabilities of the underlying H/W. ° MO ≡ How Machine Implements ISA, -Physical Implementation; -Logic Gates; -Higher Level Structures (registers, ALUs, memories, etc.) ° In CPSC321 we will study both

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Instruction Set Architecture (ISA) “... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaaw, and Brooks, 1964 An ISA encompasses: -- Organization of Storage (registers, memory) -- Primitive Data Types & Data “Structures”: Encodings & Representations (how the particular values are represented in the memory) integer, floating point, fixed point, character, arrays, etc. -- Instruction Set -- Instruction Formats -- Modes of Addressing and Accessing Data Items and Instructions -- Exceptional Conditions and their Handling Modes

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu The Instruction Set: a (the?) Critical Interface instruction set Applications/Systems Software: executable code Hardware: actual machine

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu What is “Computer Architecture”? I/O system Processor Compiler Operating System (UNIX, W2k, VAX/VMS) Applications (Netscape) Digital Design Circuit Design Instruction Set Architecture Datapath & Control Transistors IC layout Memory Hardware Software Assembler CPSC 321 ° Coordination of many levels of abstraction hide unnecessary implementation details helps us cope with enormous complexity of real systems ° Under a rapidly changing set of forces ° Design, Measurement, and Evaluation

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Example ISAs (Instruction Set Architectures) ° Digital Alpha(v1, v3) ° HP PA-RISC(v1.1, v2.0) ° Sun Sparc(v8, v9) ° SGI MIPS(MIPS I, II, III, IV, V) ° Intel(8086,80286,80386, ,Pentium, MMX, ia64)

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Impact of changing an ISA ° Early 1990’s Apple switched instruction set architecture of the Macintosh From Motorola based machines To PowerPC architecture Upside? Downside? ° Intel 80x86 Family: many implementations of same architecture Upside: program written in 1978 for 8086 can be run on latest Pentium chip Downside?

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Example: MIPS R3000 Instruction Set Architecture ° Instruction Classes: Load/Store; Computational; Jump and Branch; Floating Point - via coprocessor; Memory Management; Special, System Support. ° 3 Instruction Formats: all 32 bits wide OP Rs Rt rdsafunct OP Rs Rt Immediate OP jump target R0 - R31 PC HI LO 32 General Purpose Registers 32 bits wide n -1

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu The Big Picture Control Datapath Memory Processor “CPU” Datapath + Control Unit Input Output 1 Since 1946 all computers have had 5 components (Von Newmann Architecture) Interconnection Structures (buses)

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Forces Shapping Computer Architecture Trends Computer Architecture Technology Programming Languages Systems Software Organization History Applications Cleverness

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Forces Acting on Computer Architecture ° R-a-p-i-d Improvement in Implementation Technology: IC: integrated circuit; invented 1959 SSI  MSI  LSI  VLSI: dramatic growth in number transistors/chip  ability to create more (and bigger) FUs per processor; bigger memory  more sophisticated applications, larger databases ° Tomorrow’s Science Fiction: ubiquitous computing: computers embedded everywhere ° New Languages: Java, C++...

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Technology Trends ° In ~1985 the single-chip processor (32-bit) and the single- board computer emerged Workstations, personal computers, multiprocessors have been riding this wave since ° In the timeframe, these look like mainframes compared to single-chip computer (maybe 2 chips) DRAM YearSize Kb Kb Mb Mb Mb Mb Mb Gb DRAM chip capacity Microprocessor Logic Density

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Trends: Processor Performance ° Performance with respect to performance of VAX-11/780

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Performance Trends Microprocessors Minicomputers Mainframes Supercomputers 1995 Year Log of Performance Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year – Feature Size: shrinks 10% / yr.  Switching speed improves 1.2 / yr. –Density: improves 1.2 x / yr. –Die Area: 1.2x / yr. The lesson of RISC is to keep the ISA as simple as possible: – Shorter design cycle  fully exploit the advancing technology (~3yr) –Advanced branch prediction and pipeline techniques –Bigger and more sophisticated on-chip caches

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Technology  Dramatic Changes ° Processor logic capacity: 2  in performance every 1.5 years; clock rate: about 30% per year overall performance: 1000  in last decade ° Main Memory DRAM capacity: 2  / 2 years; 1000  size in last decade memory speed: about 10% per year cost / bit: improves about 25% per year ° Disk capacity: > 2  in size every 1.5 years cost / bit: improves about 60% per year 120  size in last decade ° Network Bandwidth Bandwidth: increasing more than 100% per year!

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu The PC in 2003 ° State-of-the-art PC two—three years from now: Processor clock speed: MegaHertz (6.0 GigaHertz) Memory capacity: -512 MegaBytes(0.5 GigaBytes) Disk capacity: -240 GigaBytes(0.24 TeraBytes) Will need new units! -Mega  Giga  Tera  Peta

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Computer Architecture Measurement and Evaluation Architecture design is iterative: – “searching” the space of possible designs – at all levels of computer systems Design Analysis Good Ideas Mediocre Ideas Bad Ideas Cost / Performance Analysis Creativity

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Processor Performance (SPEC) RISC introduction Did RISC win the technology battle and lose the market war? performance now improves ~60% per year (2x every 1.5 years)

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Applications and Languages ° CAD, CAM, CAE,... ° Lotus, DOS,... ° Multimedia,... ° The Web,... ° JAVA,... ° The Net  Ubiquitous Computing ° ???

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Hierarchy of Abstractions temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw$15,0($2) lw$16,4($2) sw$16,0($2) sw$15,4($2) IR  Imem[PC]; PC  PC + 4 High Level Language Program (e.g., C) Assembly Language Program (e.g., MIPS) Machine Language Program (MIPS) Datapath Transfer Specification Compiler Assembler Machine Interpretation °°°° reasons to use HLL language? C code Assembly code Machine code ALUOP[0:3]  InstReg[9:11] & MASK

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Levels of Organization SPARCstation 20 Processor Computer Control Datapath MemoryDevices Input Output (passive) (where programs, & data live when running) Workstation Design Target: 25% of cost on Processor 25% of cost on Memory (minimum memory size) Rest on I/O devices, power supplies, box Any computer, no matter how primitive or advanced, can be divided into five parts: 1. The input devices bring the data from the outside world into the computer. 2. These data are kept in the computer’s memory until The datapath request and process them. 4. The operation of the datapath is controlled by the computer’s controller (control unit). 5. Getting the data back to the outside world is the job of the output devices. 6. The most COMMON way to connect these 5 components together is to use a network of busses.

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Computer Organization Logic Designer's View ISA Level FUs & Interconnect ° Capabilities & Performance Characteristics of Principal Functional Units (e.g., Registers, ALU, Shifters, Logic Units,...) ° Ways in which these components are interconnected to support the ISA ° Choreography of FUs to realize the ISA ° Information flows between components ° Logic and means by which such information flow is controlled. ° Register Transfer Level (RTL) Description ° Levels of Machine Description Register Transfer Level (RTL) Gate Level (Digital Design)

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Basic Instruction Execution Cycle Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu What needs to be specified for an ISA ° Instruction Format or Encoding how is it decoded? ° Location of operands and result where other than memory? how many explicit operands? how are memory operands located? which can or cannot be in memory? ° Data type and Size ° Operations what are supported ° Successor instruction jumps, conditions, branches fetch-decode-execute is implicit! Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Example Organization: SPARC20 ° TI SuperSPARC tm TMS390Z50 in Sun SPARCstation20 ° Popular Architecture Floating-point Unit Integer Unit Inst Cache Ref MMU Data Cache Store Buffer Bus Interface SuperSPARC L2$ CC MBus Module Mbus L64852 MBus control M-S Adapter SBus DRAM Controller SBus DMA SCSI Ethernet STDIO serial kbd mouse audio RTC Boot PROM Floppy SBus Cards

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Assignments ° Readings (textbook [PeHa]) Chapter 1 [quick overview]; ° Lab #1 is already out. It is due the following week (one full week after your lab session) ° Projects teach architecture concepts AND system building skills project works correctly first time? If not, must use your analytical and deductive skills to find/fix bugs repeat until all bugs found/fixed debugging may take 1/2 of project time or more!

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu The SPARCstation 20 Memory Controller SIMM Bus Memory SIMMs Slot 1 Mbus Slot 0Mbus MSBI Slot 1SBusSlot 0SBusSlot 3SBusSlot 2SBus MBus SEC MACIO Disk Tape SCSI Bus SBus Keyboard & Mouse Floppy Disk External Bus SPARCstation 20

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu The Underlying Interconnect SPARCstation 20 Memory Controller SIMM Bus MSBI Processor/Mem Bus: MBus SECMACIO Standard I/O Bus: Sun ’ s High Speed I/O Bus: SBus Low Speed I/O Bus: External Bus SCSI Bus

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Processor and Caches SPARCstation 20 Slot 1MBus Slot 0MBus MBus Module External Cache DatapathRegisters Internal Cache Control Processor

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Main Memory SPARCstation 20 Memory Controller Memory SIMM Bus SIMM Slot 0SIMM Slot 1SIMM Slot 2SIMM Slot 3SIMM Slot 4SIMM Slot 5SIMM Slot 6SIMM Slot 7 DRAM SIMM DRAM

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Input and Output (I/O) Devices SPARCstation 20 Slot 1SBusSlot 0SBusSlot 3SBusSlot 2SBus SECMACIO Disk Tape SCSI Bus SBus Keyboard & Mouse Floppy Disk External Bus ° SCSI Bus: Standard I/O Devices ° SBus: High Speed I/O Devices ° External Bus: Low Speed I/O Device

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Standard I/O Devices SPARCstation 20 Disk Tape SCSI Bus ° SCSI = Small Computer Systems Interface ° A standard interface (IBM, Apple, HP, Sun... etc.) ° Computers and I/O devices communicate with each other ° The hard disk is one I/O device resides on the SCSI Bus

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu High Speed I/O Devices SPARCstation 20 Slot 1SBusSlot 0SBusSlot 3SBusSlot 2SBus ° SBus is SUN’s own high speed I/O bus ° SS20 has four SBus slots where we can plug- in fast I/O devices ° Example: graphics accelerator, video adaptor,..., etc. ° High speed and low speed are relative terms

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Slow Speed I/O Devices SPARCstation 20 Keyboard & Mouse Floppy Disk External Bus ° The are only four SBus slots in SS20--``seats'' are expensive ° The speed of some I/O devices is limited by human reaction time--very very slow by computer standard ° Examples: Keyboard and mouse ° No reason to use up one of the expensive SBus slot

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Summary ° All computers consist of five components Processor: (1) datapath and (2) control (3) Memory (4) Input devices and (5) Output devices ° Memory Types Cache: fast (expensive) memory are placed closer to the processor Main memory: less expensive memory--we can have more ° Interfaces are where the problems are – between functional units and between the computer and the outside world ° Need to design against constraints of performance, power, area and cost

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu Summary: Computer System Components Proc Caches Busses Memory I/O Devices: Controllers adapters Disks Displays Keyboards Networks ° All have interfaces & organizations