Instructor: Erol Sahin Y86 Instruction Set Architecture – SEQ processor CENG331: Introduction to Computer Systems 8th Lecture Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

Instruction Set Architecture Assembly Language View Processor state Registers, memory, … Instructions addl, movl, leal, … How instructions are encoded as bytes Layer of Abstraction Above: how to program machine Processor executes instructions in a sequence Below: what needs to be built Use variety of tricks to make it run fast E.g., execute multiple instructions simultaneously ISA Compiler OS CPU Design Circuit Chip Layout Application Program

Y86 Processor State Program Registers Condition Codes Program Counter Memory %eax %esi %ecx %edi OF ZF SF %edx %esp PC %ebx %ebp Program Registers Same 8 as with IA32. Each 32 bits Condition Codes Single-bit flags set by arithmetic or logical instructions OF: Overflow ZF: Zero SF:Negative Program Counter Indicates address of instruction Memory Byte-addressable storage array Words stored in little-endian byte order

Y86 Instructions Format 1--6 bytes of information read from memory Can determine instruction length from first byte Not as many instruction types, and simpler encoding than with IA32 Each accesses and modifies some part(s) of the program state

Encoding Registers Each register has 4-bit ID Same encoding as in IA32 Register ID 8 indicates “no register” Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 1 2 3 6 7 4 5

Instruction Example Addition Instruction %eax %ecx %edx %ebx %esi %edi %esp %ebp 1 2 3 6 7 4 5 Instruction Example Addition Instruction Add value in register rA to that in register rB Store result in register rB Note that Y86 only allows addition to be applied to register data Set condition codes based on result e.g., addl %eax,%esi Encoding: 60 06 Two-byte encoding First indicates instruction type Second gives source and destination registers Generic Form Encoded Representation addl rA, rB 6 rA rB

Arithmetic and Logical Operations Instruction Code Function Code Refer to generically as “OPl” Encodings differ only by “function code” Low-order 4 bytes in first instruction word Set condition codes as side effect Add addl rA, rB 6 rA rB Subtract (rA from rB) subl rA, rB 6 1 rA rB And andl rA, rB 6 2 rA rB Exclusive-Or xorl rA, rB 6 3 rA rB

Move Operations Like the IA32 movl instruction Register --> Register rrmovl rA, rB 2 rA rB Immediate --> Register irmovl V, rB 3 8 rB V Register --> Memory rmmovl rA, D(rB) 4 rA rB D Memory --> Register mrmovl D(rB), rA 5 rA rB D Like the IA32 movl instruction Simpler format for memory addresses Give different names to keep them distinct

Move Instruction Examples %eax %ecx %edx %ebx %esi %edi %esp %ebp 1 2 3 6 7 4 5 Move Instruction Examples IA32 Y86 Encoding movl $0xabcd, %edx irmovl $0xabcd, %edx 30 82 cd ab 00 00 movl %esp, %ebx rrmovl %esp, %ebx 20 43 movl -12(%ebp),%ecx mrmovl -12(%ebp),%ecx 50 15 f4 ff ff ff movl %esi,0x41c(%esp) rmmovl %esi,0x41c(%esp) 40 64 1c 04 00 00 movl $0xabcd, (%eax) — movl %eax, 12(%eax,%edx) — movl (%ebp,%eax,4),%ecx —

Jump Instructions Refer to generically as “jXX” jmp Dest 7 Jump Unconditionally Dest Refer to generically as “jXX” Encodings differ only by “function code” Based on values of condition codes Same as IA32 counterparts Encode full destination address Unlike PC-relative addressing seen in IA32 jle Dest 7 1 Jump When Less or Equal Dest jl Dest 7 2 Jump When Less Dest je Dest 7 3 Jump When Equal Dest jne Dest 7 4 Jump When Not Equal Dest jge Dest 7 5 Jump When Greater or Equal Dest jg Dest 7 6 Jump When Greater Dest

Y86 Program Stack Region of memory holding program data Stack “Bottom” Region of memory holding program data Used in Y86 (and IA32) for supporting procedure calls Stack top indicated by %esp Address of top stack element Stack grows toward lower addresses Top element is at highest address in the stack When pushing, must first decrement stack pointer When popping, increment stack pointer • Increasing Addresses %esp Stack “Top”

Stack Operations Decrement %esp by 4 pushl rA a rA 8 Decrement %esp by 4 Store word from rA to memory at %esp Like IA32 Read word from memory at %esp Save in rA Increment %esp by 4 popl rA b rA 8

Subroutine Call and Return call Dest 8 Dest Push address of next instruction onto stack Start executing instructions at Dest Like IA32 Pop value from stack Use as address for next instruction ret 9

Miscellaneous Instructions nop Don’t do anything Stop executing instructions IA32 has comparable instruction, but can’t execute it in user mode We will use it to stop the simulator halt 1

Y86 Code Generation Example First Try Write typical array code Compile with gcc -O2 -S Problem Hard to do array indexing on Y86 Since don’t have scaled addressing modes /* Find number of elements in null-terminated list */ int len1(int a[]) { int len; for (len = 0; a[len]; len++) ; return len; } L18: incl %eax cmpl $0,(%edx,%eax,4) jne L18

Y86 Code Generation Example #2 Second Try Write with pointer code Compile with gcc -O2 -S Result Don’t need to do indexed addressing /* Find number of elements in null-terminated list */ int len2(int a[]) { int len = 0; while (*a++) len++; return len; } L24: movl (%edx),%eax incl %ecx L26: addl $4,%edx testl %eax,%eax jne L24

Y86 Code Generation Example #3 IA32 Code Setup Y86 Code Setup len2: pushl %ebp xorl %ecx,%ecx movl %esp,%ebp movl 8(%ebp),%edx movl (%edx),%eax jmp L26 len2: pushl %ebp # Save %ebp xorl %ecx,%ecx # len = 0 rrmovl %esp,%ebp # Set frame mrmovl 8(%ebp),%edx # Get a mrmovl (%edx),%eax # Get *a jmp L26 # Goto entry

Y86 Code Generation Example #4 IA32 Code Loop + Finish Y86 Code Loop + Finish L24: movl (%edx),%eax incl %ecx L26: addl $4,%edx testl %eax,%eax jne L24 movl %ebp,%esp movl %ecx,%eax popl %ebp ret L24: mrmovl (%edx),%eax # Get *a irmovl $1,%esi addl %esi,%ecx # len++ L26: # Entry: irmovl $4,%esi addl %esi,%edx # a++ andl %eax,%eax # *a == 0? jne L24 # No--Loop rrmovl %ebp,%esp # Pop rrmovl %ecx,%eax # Rtn len popl %ebp ret

Y86 Program Structure Program starts at address 0 Must set up stack irmovl Stack,%esp # Set up stack rrmovl %esp,%ebp # Set up frame irmovl List,%edx pushl %edx # Push argument call len2 # Call Function halt # Halt .align 4 List: # List of elements .long 5043 .long 6125 .long 7395 .long 0 # Function len2: . . . # Allocate space for stack .pos 0x100 Stack: Program starts at address 0 Must set up stack Make sure don’t overwrite code! Must initialize data Can use symbolic names

Assembling Y86 Program Generates “object code” file eg.yo unix> yas eg.ys Generates “object code” file eg.yo Actually looks like disassembler output 0x000: 308400010000 | irmovl Stack,%esp # Set up stack 0x006: 2045 | rrmovl %esp,%ebp # Set up frame 0x008: 308218000000 | irmovl List,%edx 0x00e: a028 | pushl %edx # Push argument 0x010: 8028000000 | call len2 # Call Function 0x015: 10 | halt # Halt 0x018: | .align 4 0x018: | List: # List of elements 0x018: b3130000 | .long 5043 0x01c: ed170000 | .long 6125 0x020: e31c0000 | .long 7395 0x024: 00000000 | .long 0

Simulating Y86 Program Instruction set simulator unix> yis eg.yo Computes effect of each instruction on processor state Prints changes in state from original Stopped in 41 steps at PC = 0x16. Exception 'HLT', CC Z=1 S=0 O=0 Changes to registers: %eax: 0x00000000 0x00000003 %ecx: 0x00000000 0x00000003 %edx: 0x00000000 0x00000028 %esp: 0x00000000 0x000000fc %ebp: 0x00000000 0x00000100 %esi: 0x00000000 0x00000004 Changes to memory: 0x00f4: 0x00000000 0x00000100 0x00f8: 0x00000000 0x00000015 0x00fc: 0x00000000 0x00000018

CISC versus RISC CENG331: Introduction to Computer Systems 8th Lecture Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

CISC Instruction Sets Stack-oriented instruction set Complex Instruction Set Computer Dominant style through mid-80’s Stack-oriented instruction set Use stack to pass arguments, save program counter (IA32 but not int x86-64) Explicit push and pop instructions Arithmetic instructions can access memory addl %eax, 12(%ebx,%ecx,4) requires memory read and write Complex address calculation Condition codes Set as side effect of arithmetic and logical instructions Philosophy Add instructions to perform “typical” programming tasks

RISC Instruction Sets Fewer, simpler instructions Reduced Instruction Set Computer Internal project at IBM, later popularized by Hennessy (Stanford) and Patterson (Berkeley) Fewer, simpler instructions Might take more to get given task done Can execute them with small and fast hardware Register-oriented instruction set Many more (typically 32) registers Use for arguments, return pointer, temporaries Only load and store instructions can access memory Similar to Y86 mrmovl and rmmovl No Condition codes Test instructions return 0/1 in register

MIPS Registers

MIPS Instruction Examples Op Ra Rb Rd Fn 00000 R-R addu $3,$2,$1 # Register add: $3 = $2+$1 Op Ra Rb Immediate R-I addu $3,$2, 3145 # Immediate add: $3 = $2+3145 sll $3,$2,2 # Shift left: $3 = $2 << 2 Branch Op Ra Rb Offset beq $3,$2,dest # Branch when $3 = $2 Load/Store Op Ra Rb Offset lw $3,16($2) # Load Word: $3 = M[$2+16] sw $3,16($2) # Store Word: M[$2+16] = $3

CISC vs. RISC Original Debate Current Status Strong opinions! CISC proponents---easy for compiler, fewer code bytes RISC proponents---better for optimizing compilers, can make run fast with simple chip design Current Status For desktop processors, choice of ISA not a technical issue With enough hardware, can make anything run fast Code compatibility more important For embedded processors, RISC makes sense Smaller, cheaper, less power

Summary Y86 Instruction Set Architecture How Important is ISA Design? Similar state and instructions as IA32 Simpler encodings Somewhere between CISC and RISC How Important is ISA Design? Less now than before With enough hardware, can make almost anything go fast AMD/Intel moved away from IA32 Does not allow enough parallel execution x86-64 64-bit word sizes (overcome address space limitations) Radically different style of instruction set with explicit parallelism Requires sophisticated compilers

Instructor: Erol Sahin Logic Design and HCL CENG331: Introduction to Computer Systems 8th Lecture Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

Computing with Logic Gates Outputs are Boolean functions of inputs Respond continuously to changes in inputs With some, small delay Rising Delay Falling Delay a && b b Voltage a Time

Combinational Circuits Acyclic Network Primary Inputs Outputs Acyclic Network of Logic Gates Continously responds to changes on primary inputs Primary outputs become (after some delay) Boolean functions of primary inputs

bool eq = (a&&b)||(!a&&!b) Bit Equality Bit equal a b eq HCL Expression bool eq = (a&&b)||(!a&&!b) Generate 1 if a and b are equal Hardware Control Language (HCL) Very simple hardware description language Boolean operations have syntax similar to C logical operations We’ll use it to describe control logic for processors

Word-Level Representation Word Equality Word-Level Representation b31 Bit equal a31 eq31 b30 a30 eq30 b1 a1 eq1 b0 a0 eq0 Eq = B A Eq HCL Representation bool Eq = (A == B) 32-bit word size HCL representation Equality operation Generates Boolean value

Bit-Level Multiplexor s Bit MUX HCL Expression bool out = (s&&a)||(!s&&b) b out a Control signal s Data signals a and b Output a when s=1, b when s=0

Word-Level Representation Word Multiplexor Word-Level Representation b31 s a31 out31 b30 a30 out30 b0 a0 out0 s B A Out MUX HCL Representation int Out = [ s : A; 1 : B; ]; Select input word A or B depending on control signal s HCL representation Case expression Series of test : value pairs Output value for first successful test

HCL Word-Level Examples Minimum of 3 Words Find minimum of three input words HCL case expression Final case guarantees match int Min3 = [ A < B && A < C : A; B < A && B < C : B; 1 : C; ]; A Min3 MIN3 B C 4-Way Multiplexor D0 D3 Out4 s0 s1 MUX4 D2 D1 Select one of 4 inputs based on two control bits HCL case expression Simplify tests by assuming sequential matching int Out4 = [ !s1&&!s0: D0; !s1 : D1; !s0 : D2; 1 : D3; ];

Arithmetic Logic Unit Combinational logic Y X X + Y A L U Y X X - Y 1 A L U Y X X & Y 2 A L U Y X X ^ Y 3 A B A B A B A B OF ZF CF OF ZF CF OF ZF CF OF ZF CF Combinational logic Continuously responding to inputs Control signal selects function computed Corresponding to 4 arithmetic/logical operations in Y86 Also computes values for condition codes

Registers Stores word of data Collection of edge-triggered latches Structure D C Q+ i7 i6 i5 i4 i3 i2 i1 i0 o7 o6 o5 o4 o3 o2 o1 o0 Clock I O Clock Stores word of data Different from program registers seen in assembly code Collection of edge-triggered latches Loads input on rising edge of clock

Register Operation   y x Stores data bits State = x  State = y Output = y y Rising clock  x Input = y Output = x Stores data bits For most of time acts as barrier between input and output As clock rises, loads input

State Machine Example Accumulator circuit Comb. Logic A L U Out MUX 1 Clock In Load Accumulator circuit Load or accumulate on each cycle x0 x1 x2 x3 x4 x5 x0+x1 x0+x1+x2 x3+x4 x3+x4+x5 Clock Load In Out

Random-Access Memory Stores multiple words of memory Register file B W dstW srcA valA srcB valB valW Read ports Write port Clock Stores multiple words of memory Address input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Register identifier serves as address ID 8 implies no read or write performed Multiple Ports Can read and/or write multiple words in one cycle Each has separate address and data input/output

Register File Timing   Reading Writing Like combinational logic 2 Output data generated based on input address After some delay Writing Like register Update only as clock rises Register file A B srcA valA srcB valB 2 x x 2 y 2 Register file W dstW valW Clock x  Register file W dstW valW Clock y 2 Rising clock 

Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool: Boolean a, b, c, … int: words A, B, C, … Does not specify word size---bytes, 32-bit words, … Statements bool a = bool-expr ; int A = int-expr ;

HCL Operations Boolean Expressions Word Expressions Classify by type of value returned Boolean Expressions Logic Operations a && b, a || b, !a Word Comparisons A == B, A != B, A < B, A <= B, A >= B, A > B Set Membership A in { B, C, D } Same as A == B || A == C || A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, … in sequence Return word expression A, B, C, … for first successful test

Summary Computation Storage Performed by combinational logic Computes Boolean functions Continuously reacts to input changes Storage Registers Hold single words Loaded as clock rises Random-access memories Hold multiple words Possible multiple read or write ports Read word when address input changes Write word as clock rises

Instructor: Erol Sahin SEQuential processor implementation CENG331: Introduction to Computer Systems 8th Lecture Instructor: Erol Sahin Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

Y86 Instruction Set Byte 1 2 3 4 5 nop addl 6 subl 1 andl 2 xorl 3 1 2 3 4 5 nop addl 6 subl 1 andl 2 xorl 3 halt 1 rrmovl rA, rB 2 rA rB irmovl V, rB 3 8 rB V rmmovl rA, D(rB) 4 rA rB D jmp 7 jle 1 jl 2 je 3 jne 4 jge 5 jg 6 mrmovl D(rB), rA 5 rA rB D OPl rA, rB 6 fn rA rB jXX Dest 7 fn Dest call Dest 8 Dest ret 9 pushl rA A rA 8 popl rA B rA 8

SEQ Hardware Structure newPC SEQ Hardware Structure PC valE , valM Write back valM State Program counter register (PC) Condition code register (CC) Register File Memories Access same memory space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter Data Data Memory memory memory Addr , Data valE CC CC Execute Bch ALU ALU aluA , aluB valA , valB Decode srcA , srcB dstA , dstB Register Register A A B B Register Register M M file file file file E E icode , ifun valP rA , rB valC Instruction Instruction PC PC Fetch memory memory increment increment PC

SEQ Stages Fetch Decode Execute Memory Write Back PC newPC SEQ Stages PC valE , valM Write back valM Fetch Read instruction from instruction memory Decode Read program registers Execute Compute value or address Memory Read or write data Write Back Write program registers PC Update program counter Data Data Memory memory memory Addr , Data valE CC CC Execute Bch ALU ALU aluA , aluB valA , valB Decode srcA , srcB dstA , dstB Register Register A A B B Register Register M M file file file file E E icode , ifun valP rA , rB valC Instruction Instruction PC PC Fetch memory memory increment increment PC

Instruction Decoding Instruction Format Instruction byte icode:ifun 5 rA rB D icode ifun valC Optional Instruction Format Instruction byte icode:ifun Optional register byte rA:rB Optional constant word valC

Executing Arith./Logical Operation OPl rA, rB 6 fn rA rB Fetch Read 2 bytes Decode Read operand registers Execute Perform operation Set condition codes Memory Do nothing Write back Update register PC Update Increment PC by 2

Stage Computation: Arith/Log. Ops OPl rA, rB icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory R[rB]  valE Write back Write back result PC  valP PC update Update PC Formulate instruction execution as sequence of simple steps Use same general form for all instructions

Executing rmmovl Fetch Decode Execute Memory Write back PC Update 4 rB rmmovl rA, D(rB) 4 rA rB D Fetch Read 6 bytes Decode Read operand registers Execute Compute effective address Memory Write to memory Write back Do nothing PC Update Increment PC by 6

Stage Computation: rmmovl rmmovl rA, D(rB) icode:ifun  M1[PC] rA:rB  M1[PC+1] valC  M4[PC+2] valP  PC+6 Fetch Read instruction byte Read register byte Read displacement D Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB + valC Execute Compute effective address M4[valE]  valA Memory Write value to memory Write back PC  valP PC update Update PC Use ALU for address computation

Executing popl Fetch Decode Execute Memory Write back PC Update popl rA b rA 8 Fetch Read 2 bytes Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2

Stage Computation: popl popl rA icode:ifun  M1[PC] rA:rB  M1[PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[%esp] valB  R [%esp] Decode Read stack pointer valE  valB + 4 Execute Increment stack pointer valM  M4[valA] Memory Read from stack R[%esp]  valE R[rA]  valM Write back Update stack pointer Write back result PC  valP PC update Update PC Use ALU to increment stack pointer Must update two registers Popped value New stack pointer

Executing Jumps Fetch Decode Execute Memory Write back PC Update jXX Dest 7 fn Dest XX fall thru: target: Not taken Taken Fetch Read 5 bytes Increment PC by 5 Decode Do nothing Execute Determine whether to take branch based on jump condition and condition codes Memory Do nothing Write back PC Update Set PC to Dest if branch taken or to incremented PC if not branch

Stage Computation: Jumps jXX Dest icode:ifun  M1[PC] valC  M4[PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Fall through address Decode Bch  Cond(CC,ifun) Execute Take branch? Memory Write back PC  Bch ? valC : valP PC update Update PC Compute both addresses Choose based on setting of condition codes and branch condition

Executing call Fetch Decode Execute Memory Write back PC Update call Dest 8 Dest XX return: target: Fetch Read 5 bytes Increment PC by 5 Decode Read stack pointer Execute Decrement stack pointer by 4 Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest

Stage Computation: call call Dest icode:ifun  M1[PC] valC  M4[PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Compute return point valB  R[%esp] Decode Read stack pointer valE  valB + –4 Execute Decrement stack pointer M4[valE]  valP Memory Write return value on stack R[%esp]  valE Write back Update stack pointer PC  valC PC update Set PC to destination Use ALU to decrement stack pointer Store incremented PC

Executing ret Fetch Decode Execute Memory Write back PC Update 9 return: XX Fetch Read 1 byte Decode Read stack pointer Execute Increment stack pointer by 4 Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address

Stage Computation: ret icode:ifun  M1[PC] Fetch Read instruction byte valA  R[%esp] valB  R[%esp] Decode Read operand stack pointer valE  valB + 4 Execute Increment stack pointer valM  M4[valA] Memory Read return address R[%esp]  valE Write back Update stack pointer PC  valM PC update Set PC to return address Use ALU to increment stack pointer Read return address from memory

Computation Steps All instructions follow same general pattern OPl rA, rB Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB rA:rB  M1[PC+1] Read register byte valC [Read constant word] valP valP  PC+2 Compute next PC Decode valA, srcA valA  R[rA] Read operand A valB, srcB valB  R[rB] Read operand B Execute valE valE  valB OP valA Perform ALU operation Cond code Set CC Set condition code register Memory valM [Memory read/write] Write back dstE R[rB]  valE Write back ALU result dstM [Write back memory result] PC update PC PC  valP Update PC All instructions follow same general pattern Differ in what gets computed on each step

Irmovl: Computation Steps irmovl V, rB Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB rA:rB  M1[PC+1] Read register byte valC valC M4[PC+2] [Read constant word] valP valP  PC+6 Compute next PC Decode valA, srcA valB, srcB Execute valE valE  0 + valC Perform ALU operation Cond code Memory valM Write back dstE R[rB]  valE Write back ALU result dstM PC update PC PC  valP Update PC All instructions follow same general pattern Differ in what gets computed on each step

Computation Steps All instructions follow same general pattern call Dest Fetch icode,ifun icode:ifun  M1[PC] Read instruction byte rA,rB [Read register byte] valC valC  M4[PC+1] Read constant word valP valP  PC+5 Compute next PC Decode valA, srcA [Read operand A] valB, srcB valB  R[%esp] Read operand B Execute valE valE  valB + –4 Perform ALU operation Cond code [Set condition code reg.] Memory valM M4[valE]  valP [Memory read/write] Write back dstE R[%esp]  valE [Write back ALU result] dstM Write back memory result PC update PC PC  valC Update PC All instructions follow same general pattern Differ in what gets computed on each step

Computed Values Fetch Decode Execute Memory icode Instruction code ifun Instruction function rA Instr. Register A rB Instr. Register B valC Instruction constant valP Incremented PC Decode srcA Register ID A srcB Register ID B dstE Destination Register E dstM Destination Register M valA Register value A valB Register value B Execute valE ALU result Bch Branch flag Memory valM Value from memory

SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values

Fetch Logic Predefined Blocks PC: Register containing PC Instruction memory: Read 6 bytes (PC to PC+5) Split: Divide instruction byte into icode and ifun Align: Get fields for rA, rB, and valC

Fetch Logic Control Logic Instr. Valid: Is this instruction valid? Need regids: Does this instruction have a register bytes? Need valC: Does this instruction have a constant word?

Fetch Control Logic bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL };

Decode Logic Register File Control Logic Read ports A, B Write ports E, M Addresses are register IDs or 8 (no access) Control Logic srcA, srcB: read port addresses dstA, dstB: write port addresses

A Source OPl rA, rB valA  R[rA] Decode Read operand A rmmovl rA, D(rB) popl rA valA  R[%esp] Read stack pointer jXX Dest No operand call Dest ret int srcA = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : rA; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ];

E Destination None R[%esp]  valE Update stack pointer R[rB]  valE OPl rA, rB Write-back rmmovl rA, D(rB) popl rA jXX Dest call Dest ret Write back result int dstE = [ icode in { IRRMOVL, IIRMOVL, IOPL} : rB; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't need register ];

Execute Logic Units Control Logic ALU CC bcond Implements 4 required functions Generates condition code values CC Register with 3 condition code bits bcond Computes branch flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute?

ALU A Input valE  valB + –4 Decrement stack pointer No operation Increment stack pointer valE  valB + valC Compute effective address valE  valB OP valA Perform ALU operation OPl rA, rB Execute rmmovl rA, D(rB) popl rA jXX Dest call Dest ret int aluA = [ icode in { IRRMOVL, IOPL } : valA; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ];

ALU Operation valE  valB + –4 Decrement stack pointer No operation Increment stack pointer valE  valB + valC Compute effective address valE  valB OP valA Perform ALU operation OPl rA, rB Execute rmmovl rA, D(rB) popl rA jXX Dest call Dest ret int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ];

Memory Logic Memory Control Logic Reads or writes memory word Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address Mem. data.: Select data

Memory Address OPl rA, rB Memory rmmovl rA, D(rB) popl rA jXX Dest call Dest ret No operation M4[valE]  valA Write value to memory valM  M4[valA] Read from stack M4[valE]  valP Write return value on stack Read return address int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE; icode in { IPOPL, IRET } : valA; # Other instructions don't need address ];

Memory Read OPl rA, rB Memory rmmovl rA, D(rB) popl rA jXX Dest call Dest ret No operation M4[valE]  valA Write value to memory valM  M4[valA] Read from stack M4[valE]  valP Write return value on stack Read return address bool mem_read = icode in { IMRMOVL, IPOPL, IRET };

PC Update Logic New PC Select next value of PC

PC Update OPl rA, rB rmmovl rA, D(rB) popl rA jXX Dest call Dest ret PC  valP PC update Update PC PC  Bch ? valC : valP PC  valC Set PC to destination PC  valM Set PC to return address int new_pc = [ icode == ICALL : valC; icode == IJXX && Bch : valC; icode == IRET : valM; 1 : valP; ];

SEQ Operation State Combinational Logic PC register Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic Memory reads Instruction memory

SEQ Operation #2 state set according to second irmovl instruction combinational logic starting to react to state changes

SEQ Operation #3 state set according to second irmovl instruction combinational logic generates results for addl instruction

SEQ Operation #4 state set according to addl instruction combinational logic starting to react to state changes

SEQ Operation #5 state set according to addl instruction combinational logic generates results for je instruction

SEQ Summary Implementation Limitations Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logic Limitations Too slow to be practical In one cycle, must propagate through instruction memory, register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle