In-memory Accelerators with Memristors Yuval Cassuto Koby Crammer Avinoam Kolodny Technion – EE ICRI-CI Retreat May 8, 2013 PU MEM NVM

3-way Collaboration A. Kolodny Y. Cassuto K. Crammer ML App. Devices Representations

The Data Deluge Mobile, Cloud Computing

Non-Volatile Memories 101 functionality density PROMEPROM E 2 PROM Memristors Mass Storage NAND Flash + logic!

Non-Volatile Memories 101 functionality density PROMEPROM E 2 PROM NAND Flash Main Memory Memristors + logic!

Memristor Crossbar Arrays

VgVg RLRL VoVo c ij c ij =0  high resistance  low current sensed c ij =1  low resistance  high current sensed Memristor Readout

VgVg RLRL VoVo Desired Path Sneak Path 1 1 c ij =0  high resistance  low current sensed c ij =1  low resistance  high current sensed Sneak Paths

Two Solutions Poor capacity High read power

Our Mixed Solution YC, E. Yaakobi, S. Kvatinsky, ISIT 2013 b

Results Summary YC, E. Yaakobi, S. Kvatinsky, ISIT ) Fixed partition2) Sliding window Higher capacity e.g vs for b=7 Column-by-column encoding, optimal

In-memory Acceleration Motivation: transfer bottlenecks Method: compute in memory, transfer results What to compute?

Similarity Inner Products Hyp. 1 Hyp. 2 Trial ∑ = ∑ =5 More similar Less similar

Inner Products in ML

Memristor Inner Products (ideal) Trial Hyp R= ∞ G T =3/2R R 2R Output = 3· ConstInner product

Ideal Inner Products Hamming distance in 3 measurements : 1 2 3

Real Inner Products Error terms

Evaluation Can compute Hamming distance as if ideal –3 measurements –plus arithmetic Cannot compute inner product precisely in 1 measurement

Continued Research Transform input vectors to maximize precision ML Theory: provable optimality (information-theoretic learning) ML Practice: optimize transformations within real ML algorithms

Multi-level Inner Products R= ∞ R1R1 R1+R2R1+R2 R2R2 R3R3 R3+R1R3+R1 2R 3

Thank You!