EE 5340 Semiconductor Device Theory Lecture 07 – Spring 2011 Professor Ronald L. Carter

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EE 5340 Semiconductor Device Theory Lecture 07 – Spring 2011 Professor Ronald L. Carter

©rlc L07-11Feb20112 Second Assignment Submit a signed copy of the document posted at

©rlc L07-11Feb20113 Test 1 – Tuesday 22Feb11 11 AM Room 129 ERB Covering Lectures 1 through 9 Open book - 1 legal text or ref., only. You may write notes in your book. Calculator allowed A cover sheet will be included with full instructions. For examples see

©rlc L07-11Feb20114 Diffusion of carriers In a gradient of electrons or holes,  p and  n are not zero Diffusion current,  J =  J p +  J n (note D p and D n are diffusion coefficients)

©rlc L07-11Feb20115 Diffusion of carriers (cont.) Note (  p) x has the magnitude of dp/dx and points in the direction of increasing p (uphill) The diffusion current points in the direction of decreasing p or n (downhill) and hence the - sign in the definition of  J p and the + sign in the definition of  J n

©rlc L07-11Feb20116 Diffusion of Carriers (cont.)

©rlc L07-11Feb20117 Current density components

©rlc L07-11Feb20118 Total current density

©rlc L07-11Feb20119 Doping gradient induced E-field If N = N d -N a = N(x), then so is E f -E fi Define  = (E f -E fi )/q = (kT/q)ln(n o /n i ) For equilibrium, E fi = constant, but for dN/dx not equal to zero, E x = -d  /dx =- [d(E f -E fi )/dx](kT/q) = -(kT/q) d[ln(n o /n i )]/dx = -(kT/q) (1/n o )[dn o /dx] = -(kT/q) (1/N)[dN/dx], N > 0

©rlc L07-11Feb Induced E-field (continued) Let V t = kT/q, then since n o p o = n i 2 gives n o /n i = n i /p o E x = - V t d[ln(n o /n i )]/dx = - V t d[ln(n i /p o )]/dx = - V t d[ln(n i /|N|)]/dx, N = -N a < 0 E x = - V t (-1/p o )dp o /dx = V t (1/p o )dp o /dx = V t (1/N a )dN a /dx

©rlc L07-11Feb The Einstein relationship For E x = - V t (1/n o )dn o /dx, and J n,x = nq  n E x + qD n (dn/dx) = 0 This requires that nq  n [V t (1/n)dn/dx] = qD n (dn/dx) Which is satisfied if

©rlc L07-11Feb Silicon Planar Process 1 M&K 1 Fig. 2.1 Basic fabrication steps in the silicon planar process: (a) oxide formation, (b) oxide removal, (c) deposition of dopant atoms, (d) diffusion of dopant atoms into exposed regions of silicon.

©rlc L07-11Feb LOCOS Process 1 1 Fig 2.26 LOCal Oxidation of Silicon (LOCOS). (a) Defined pattern consisting of stress-relief oxide and Si 3 N 4 where further oxidation is not desired, (b) thick oxide layer grown over the bare silicon region, (c) stress- relief oxide and Si 3 N 4 removed by etching, (d) scanning electron micrograph (5000 X) showing LOCOS- processed wafer at (b).

©rlc L07-11Feb Al Interconnects 1 1 Figure 2.33 (p. 104) A thin layer of aluminum can be used to connect various doped regions of a semiconductor device. 1

©rlc L07-11Feb Ion Implantation 1 1 Figure 2.15 (p. 80) In ion implantation, a beam of high-energy ions strikes selected regions of the semiconductor surface, penetrating into these exposed regions.

©rlc L07-11Feb Phosphorous implant Range (M&K 1 Figure 2.17) Projected range R p and its standard devia- tion  R p for implantation of phosphorus into Si, SiO 2, Si 3 N 4, and Al [M&K ref 11].

©rlc L07-11Feb Implant and Diffusion Profiles Figure Complementary- error-function and Gaussian distribu- tions; the vertical axis is normalized to the peak con- centration Cs, while the horizon- tal axis is normal- ized to the char- acteristic length

©rlc L07-11Feb References 1 and M&K Device Electronics for Integrated Circuits, 2 ed., by Muller and Kamins, Wiley, New York, See Semiconductor Device Fundamentals, by Pierret, Addison-Wesley, 1996, for another treatment of the  model. 2 Physics of Semiconductor Devices, by S. M. Sze, Wiley, New York, and ** Semiconductor Physics & Devices, 2nd ed., by Neamen, Irwin, Chicago, Fundamentals of Semiconductor Theory and Device Physics, by Shyh Wang, Prentice Hall, 1989.