ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS Transistor ECE442: Digital Electronics

CSUN, Spring-2010-Zahid Review: Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid The MOS Transistor Polysilicon Aluminum

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers Gate oxide n+ SourceDrain p substrate Bulk (Body) p+ stopper Field-Oxide (SiO 2 ) n+ Polysilicon Gate L W

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Transistor Layout

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Region of Operations

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Transistor Operation

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Triode Region-1

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Triode Region-2

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid NMOS Active (Saturation) Region

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Switch Model of NMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Switch Model of PMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | > | V DD – | V T | || V GS | < | V DD – |V T | | Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’) R on

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Threshold Voltage Concept S D p substrate B G V GS + - n+ depletion region n channel The value of V GS where strong inversion occurs is called the threshold voltage, V T

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid The Threshold Voltage V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) where V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process l Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V SB is the source-bulk voltage  F = -  T ln(N A /n i ) is the Fermi potential (  T = kT/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i  1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon)  =  (2q  si N A )/C ox is the body-effect coefficient (impact of changes in V SB ) (  si =1.053x F/m is the permittivity of silicon; C ox =  ox /t ox is the gate oxide capacitance with  ox =3.5x F/m)

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid The Body Effect V BS (V) V T (V) l V SB is the substrate bias voltage (normally positive for n- channel devices with the body tied to ground) l A negative bias causes V T to increase from 0.45V to 0.85V

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Transistor in Linear Mode S D B G n+ Assuming V GS > V T V GS V DS IDID x V(x) -+ The current is a linear function of both V GS and V DS

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron)  When V DS  V GS – V T I D = k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where k’ n =  n C ox =  n  ox /t ox = is the process transconductance parameter (  n is the carrier mobility (m 2 /Vsec)) k n = k’ n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Transistor in Saturation Mode S D B G V GS V DS > V GS - V T IDID V GS - V T -+ n+ Pinch-off Assuming V GS > V T V DS The current remains constant (transistor saturates)

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Voltage-Current Relation: Saturation Mode For long channel devices  When V DS  V GS – V T I D ’ = (k’ n /2) W/L [(V GS – V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS – V T  However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D ’ (1 + V DS ) where is the channel-length modulation (varies with the inverse of the channel length)

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Channel Length Modulation

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Channel Length Modulation

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Current Determinates  For a fixed V DS and V GS (> V T ), I DS is a function of l the distance between the source and drain – L l the channel width – W l the threshold voltage – V T l the thickness of the SiO 2 – t ox l the dielectric of the gate insulator (e.g., SiO 2 ) –  ox l the carrier mobility -for NMOS:  n = 500 cm 2 /V-sec -for PMOS:  p = 180 cm 2 /V-sec

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Long Channel I-V Plot (NMOS) I D (A) V DS (V) X V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Long Channel I-V Plot (NMOS) I D (A) V DS (V) X V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V LinearSaturation V DS = V GS - V T Quadratic dependence NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.43V cut-off 0.57V1.07V2.07V 1.57V

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Short Channel Effects  (V/  m)  n (m/s)  sat =10 5 Constant velocity Constant mobility (slope =  ) l For an NMOS device with L of.25  m, only a couple of volts difference between D and S are needed to reach velocity saturation c= c= l Behavior of short channel device mainly due to l Velocity saturation – the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 5

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Voltage-Current Relation: Velocity Saturation For short channel devices  Linear: When V DS  V GS – V T I D =  (V DS ) k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where  (V) = 1/(1 + (V/  c L)) is a measure of the degree of velocity saturation  Saturation: When V DS = V DSAT  V GS – V T I DSat =  (V DSAT ) k’ n W/L [(V GS – V T )V DSAT – V DSAT 2 /2]

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Velocity Saturation Effects Long channel devices Short channel devices V DSAT V GS -V T l V DSAT < V GS – V T so the device enters saturation before V DS reaches V GS – V T and operates more often in saturation For short channel devices and large enough V GS – V T l I DSAT has a linear dependence w.r.t V GS so a reduced amount of current is delivered for a given control voltage V GS = V DD

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Short Channel I-V Plot (NMOS) I D (A) V DS (V) X V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V Linear dependence NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.43V Early Velocity Saturation LinearSaturation

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS I D -V GS Characteristics V GS (V) I D (A) long-channel quadratic short-channel linear l Linear (short- channel) versus quadratic (long- channel) dependence of I D on V GS in saturation l Velocity-saturation causes the short- channel device to saturate at substantially smaller values of V DS resulting in a substantial drop in current drive (for V DS = 2.5V, W/L = 1.5) X 10 -4

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid Short Channel I-V Plot (PMOS) I D (A) V DS (V) X V GS = -1.0V V GS = -1.5V V GS = -2.0V V GS = -2.5V PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V l All polarities of all voltages and currents are reversed

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid The MOS Current-Source Model V T0 (V)  (V 0.5 )V DSAT (V)k’(A/V 2 ) (V -1 ) NMOS x PMOS x SD G B IDID I D = 0 for V GS – V T  0 I D = k’ W/L [(V GS – V T )V min –V min 2 /2](1+ V DS ) for V GS – V T  0 with V min = min(V GS – V T, V DS, V DSAT ) and V GT = V GS - V T l Determined by the voltages at the four terminals and a set of five device parameters

ECE442: Digital ElectronicsCSUN, Spring-2010-Zahid MOS Capacitance