©2011 Gary Smith EDA, Inc.All Rights Reserved. Reality and Responsibility in the EDA Market (EDP 2011) ©2011 Gary Smith EDA, Inc.All Rights Reserved.

Slides:



Advertisements
Similar presentations
Figure DESN1 Impact of Design Technology on SOC Consumer Portable Implementation Cost Software Virtual Prototype Intelligent Testbench Reusable Platform.
Advertisements

ITRS Design ITWG ITRS Design + System Drivers December 3, 2010 Design ITWG 1.Software, system level design productivity critical to roadmap 2. Manufacturability.
ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma.
Presenter : Shao-Chieh Hou VLSI Design, Automation and Test, VLSI-DAT 2007.
SOC Design: From System to Transistor
ECOE 560 Design Methodologies and Tools for Software/Hardware Systems Spring 2004 Serdar Taşıran.
February 28 – March 3, 2011 Stepwise Refinement and Reuse: The Key to ESL Ashok B. Mehta Senior Manager (DTP/SJDMP) TSMC Technology, Inc. Mark Glasser.
EDP Trends in AMS Design Methodology or Analog Design Flow, an Oxymoron ? Gary Smith Chief Analyst EDA Gartner Dataquest.
The Future of Formal: Academic, IC, EDA, and Software Perspectives Ziyad Hanna VP of Research and Chief Architect Jasper Design Automation Ziyad Hanna.
MICROELETTRONICA Design methodologies Lection 8. Design methodologies (general) Three domains –Behavior –Structural –physic Three levels inside –Architectural.
Design For Verification Synopsys Inc, April 2003.
1 HW/SW Partitioning Embedded Systems Design. 2 Hardware/Software Codesign “Exploration of the system design space formed by combinations of hardware.
IP Re-Use: The Key Challenge in SOC (System- on-Chip) Product Development D Y Yang Chairman, Taiwan SoC Consortium Jan. 14, 2003.
Behavioral Design Outline –Design Specification –Behavioral Design –Behavioral Specification –Hardware Description Languages –Behavioral Simulation –Behavioral.
Tejas Bhatt and Dennis McCain Hardware Prototype Group, NRC/Dallas Matlab as a Development Environment for FPGA Design Tejas Bhatt June 16, 2005.
ELEN468 Lecture 11 ELEN468 Advanced Logic Design Lecture 1Introduction.
Reconfigurable Computing in the Undergraduate Curriculum Jason D. Bakos Dept. of Computer Science and Engineering University of South Carolina.
6/30/2015HY220: Ιάκωβος Μαυροειδής1 Moore’s Law Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips.
EE694v-Verification-Lect5-1- Lecture 5 - Verification Tools Automation improves the efficiency and reliability of the verification process Some tools,
ECE 699: Lecture 2 ZYNQ Design Flow.
In Search of an ESL Methodology EDP 2006 Gary Smith Chief Analyst Design & Engineering.
Hardware/Software Partitioning Witawas Srisa-an Embedded Systems Design and Implementation.
Test and Verification Solutions116 th April 2010 Silicon South West, “Testing Times” The Economics of Verification Mike Bartley, TVS.
© 2011 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Xilinx Tool Flow.
Role of Standards in TLM driven D&V Methodology
I N V E N T I V EI N V E N T I V E EDA360 - Is End-to-End Design a Riddle, a Rebus, or a Reality? April 6, 2011.
Chap. 1 Overview of Digital Design with Verilog. 2 Overview of Digital Design with Verilog HDL Evolution of computer aided digital circuit design Emergence.
Why do so many chips fail? Ira Chayut, Verification Architect (opinions are my own and do not necessarily represent the opinion of my employer)
UNIT – II ARCHITECTING WEB SERVICES. WHAT ARE WEB SERVICES ? Web Services are loosely coupled, contracted components that communicate via XML-based interfaces.
ON LINE TEST GENERATION AND ANALYSIS R. Šeinauskas Kaunas University of Technology LITHUANIA.
1 Designing for 65nm and Beyond Where’s The Revolution ?!? Greg Spirakis Absolutely, positively not working for Intel (or anyone else) EDP 2005.
1 Integration Verification: Re-Create or Re-Use? Nick Gatherer Trident Digital Systems.
May 17, USB Semiconductor IP How to Integrate USB into Your Design Eric Huang inSilicon Corporation.
Copyright © 2002 Qualis Design Corporation Industry and Textbook Overview Qualis Design Corporation PO Box 4444 Beaverton, Oregon USA Phone:
System Design with CoWare N2C - Overview. 2 Agenda q Overview –CoWare background and focus –Understanding current design flows –CoWare technology overview.
IEEE Standards for Design Automation: Their Impact on the Semiconductor Industry Karen Bartleson Sr. Director, Community Marketing, Synopsys, Inc. Vice.
The Engineering Design Process * The "Engineering Design Process" is a general outline of steps that aid in the development, construction and/or manufacture.
The Macro Design Process The Issues 1. Overview of IP Design 2. Key Features 3. Planning and Specification 4. Macro Design and Verification 5. Soft Macro.
Mahapatra-Texas A&M-Fall'001 How to plan on project work? An attempt to consolidate your thought to gear up project activities.
1. CAD Challenges for Leading-Edge Multimedia Designs Ira Chayut, Verification Architect (opinions are my own and do not necessarily represent the opinion.
1 IMEC / KHBO June 2004 Micro-electronics SystemC Dorine Gevaert.
© 2006 Synopsys, Inc. (1) CONFIDENTIAL Simulation and Formal Verification: What is the Synergy? Carl Pixley Disclaimer: These opinions are mine alone and.
Business Trends and Design Methodologies for IP Reuse Allen C.-H. Wu Department of Computer Science Tsing Hua University Hsinchu, Taiwan, R.O.C {
EE3A1 Computer Hardware and Digital Design
1 Yield Analysis and Increasing Engineering Efficiency Spotfire Users Conference 10/15/2003 William Pressnall, Scott Lacey.
2D/3D Integration Challenges: Dynamic Reconfiguration and Design for Reuse.
An Overview of Hardware Design Methodology Ian Mitchelle De Vera.
FMCAD 2027: Will the FM Have a Real Impact on the CAD? Carl Pixley Disclaimer: These opinions are mine alone and not necessarily Synopsys’. Also, I tend.
M.Mohajjel. Digital Systems Advantages Ease of design Reproducibility of results Noise immunity Ease of Integration Disadvantages The real world is analog.
Teaching The Principles Of System Design, Platform Development and Hardware Acceleration Tim Kranich
Embedded Product Design. The Initial Concept of a Product l Top-level management –Composed primarily of engineers l Marketing –Feedback from customers.
CHAPTER 1 Introduction to ECADD DENC 2533 ECADD. FIRST!!!! Visit my website at and choose Teaching TAB and click at the ECADD subjectwww.asyrani.com.
Software Systems Division (TEC-SW) ASSERT process & toolchain Maxime Perrotin, ESA.
Real-Time System-On-A-Chip Emulation.  Introduction  Describing SOC Designs  System-Level Design Flow  SOC Implemantation Paths-Emulation and.
DUSD(Labs) GSRC Calibrating Achievable Design 11/02.
ISCUG Keynote May 2008 Acknowledgements to the TI-Nokia ESL forum (held Jan 2007) and to James Aldis, TI and OSCI TLM WG Chair 1 SystemC: Untapped Value.
0 Actuarial Software VIPitech SEB Estonia Experience Piret Raukas Jaanus Sibul.
Tablet Device Market m Shohei MIURA June 24, 2011Colloquium1.
DAC50, Designer Track, 156-VB543 Parallel Design Methodology for Video Codec LSI with High-level Synthesis and FPGA-based Platform Kazuya YOKOHARI, Koyo.
SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.
EMT 351/4 DIGITAL IC DESIGN Week # 1 EDA & HDL.
ASIC Design Methodology
Some Historical Context And Some Prognostication
Andes Technology Innovate SOC ProcessorsTM
Cadence Low-Power Solution
IP – Based Design Methodology
Matlab as a Development Environment for FPGA Design
ITRS Roadmap Design Process Open Discussion EDP 2001
ECE 699: Lecture 3 ZYNQ Design Flow.
TimeLess Design Automation
Presentation transcript:

©2011 Gary Smith EDA, Inc.All Rights Reserved. Reality and Responsibility in the EDA Market (EDP 2011) ©2011 Gary Smith EDA, Inc.All Rights Reserved.

Has anyone actually seen this flow ? Behavioral Level Design Architectural Level Design ESLESL Verification RT Level Level Design IC CAD Verification Tape Out

©2011 Gary Smith EDA, Inc.All Rights Reserved. Reality

©2011 Gary Smith EDA, Inc.All Rights Reserved. Or is this more like it ? Behavioral Level Design Architectural Level Design RT Level Level Design IC CAD Verification ESLESL Tape Out Again Tape Out Again

©2011 Gary Smith EDA, Inc.All Rights Reserved. Let’s break the Design Flow into its parts In the beginning you have a Platform That gives you 70% to 90% of your gates Then you design the remaining 40 or 100 million gates Which brings up the subject of IP

©2011 Gary Smith EDA, Inc.All Rights Reserved. Platform Based Design You didn’t really think you started a 400 million gate SoC from scratch did you ? Your Platform is usually your last design. Oh you don’t have one ? Then you buy one from your friendly Semiconductor vendor (i.e. TI’s OMAP, Qualcomm’s Snapdragon, or NVIDIA’s Tegra).

©2011 Gary Smith EDA, Inc.All Rights Reserved. Lesson #1

©2011 Gary Smith EDA, Inc.All Rights Reserved. That gives you 70% to 90% of your gates The Platform is the “known” part of the design. Therefore that is the major IP market (you need to “know” the design before you can make an IP for it). That is the foundation of your design, it doesn’t give you competitive advantage.

©2011 Gary Smith EDA, Inc.All Rights Reserved. Lesson #2

©2011 Gary Smith EDA, Inc.All Rights Reserved. Then you design the remaining 40 or 100 million gates 100 million is a lot of gates to design ! So it isn’t just gluing a bunch of IP together after all. Processer IP sells here, which is why ARM is the #1 IP supplier. As does library based IP, which is why Synopsys is #2.

©2011 Gary Smith EDA, Inc.All Rights Reserved. Lesson #3

©2011 Gary Smith EDA, Inc.All Rights Reserved. Which brings up the subject of IP ITRS 1997 – Small Blocks - 2,500 gates to 74,999 gates ITRS 1999 – Large Blocks - 75,000 gates to 1,000,000 gates ITRS 2007 Very Large Blocks - Over 1,000,000 gates

©2011 Gary Smith EDA, Inc.All Rights Reserved. Which brings up the subject of IP #2 Small Blocks - Sold primarily as libraries, with the exception of some analog blocks. Large Blocks - Some blocks are reconfigurable, for example memory. Very Large Blocks - Most blocks are “Modifiable” (you can add or remove Large Blocks without affecting the verification of the remaining blocks). - A high percentage of the Very Large Blocks are designed In-House, not by 3 rd party IP providers.

©2011 Gary Smith EDA, Inc.All Rights Reserved. Getting Back to The Flow So there are two flows - The design of the Platform - The design of the new block that gives you the competitive advantage. The Flows look the same but are either done by different design teams (Purchased Platform) or at a different time (In-House developed Platform).

©2011 Gary Smith EDA, Inc.All Rights Reserved. The Basic ESL Flow is The Three Virtual Prototypes The Architect’s Workbench SVP - The Silicon Virtual Prototype SWVP - The Software Virtual Prototype HW/SW Partitioning Design Verification Behavioral Level Architectural Level

©2011 Gary Smith EDA, Inc.All Rights Reserved. This Looks Better The Three Virtual Prototypes The Architect’s Workbench SVP - The Silicon Virtual Prototype SWVP - The Software Virtual Prototype HW/SW Partitioning Design Intent Manual Verification Behavioral Level Architectural Level Architect picks the Platform and the processors Architect picks the Software language and the OS

©2011 Gary Smith EDA, Inc.All Rights Reserved. Then Down to RTL and real Code RTL Implementation SVP - The Silicon Virtual Prototype SWVP - The Software Virtual Prototype ESL Architectural Level Golden RTL Net List Drivers and Middleware DESIGNDESIGN DESIGNDESIGN VERIFICATIONVERIFICATION VERIFICATIONVERIFICATION SystemCC++/C C/Assembly Code System Verilog/ VHDL

©2011 Gary Smith EDA, Inc.All Rights Reserved. Or This RTL Implementation SVP - The Silicon Virtual Prototype SWVP - The Software Virtual Prototype ESL Architectural Level Golden RTL Net List Drivers and Middleware DESIGNDESIGN DESIGNDESIGN VERIFICATIONVERIFICATION VERIFICATIONVERIFICATION Verification = Down, Add Assertions, Up – Down – Up – etc. MANUALMANUAL

©2011 Gary Smith EDA, Inc.All Rights Reserved. Responsibilit y

©2011 Gary Smith EDA, Inc.All Rights Reserved. Responsibility - the Short Form Lucio Lanza’s IC CAD speech All of the members of the Semiconductor Infrastructure have their individual responsibilities. We are all being measured by Moore’s Law.

©2011 Gary Smith EDA, Inc.All Rights Reserved. EDA’s Responsibility EDA is responsible for developing the design tools that enable the IC design process.

©2011 Gary Smith EDA, Inc.All Rights Reserved. EDA’s Responsibility EDA is responsible for developing the design tools that enable the IC design process. - Or - EDA is responsible for developing the design tools that enable the IC design process, at a design cost that allows the ecosystem to operate at a profit.

©2011 Gary Smith EDA, Inc.All Rights Reserved. What I’m not Saying This is not about the cost of EDA tools; that’s lunch money. What I’m talking about is the level of automation. The costs are in the engineers needed to do the design.

©2011 Gary Smith EDA, Inc.All Rights Reserved. ITRS Cost Chart 2010 (in Millions of Dollars) IC Implementation Tool Set RTL Functional Verif. Tool Suite Transaction Level Modeling Very Large Block Reuse SMP Parallel Processing Intelligent Testbench Many Core Devel. Tools AMP Parallel ProcessingExecutable Specification Silicon Virtual Prototype System Design Automation Software Virtual Prototype Concurrent Memory Source: Gary Smith EDA, April 2010 Green: Start-Ups stop red: most SoC design stops

©2011 Gary Smith EDA, Inc.All Rights Reserved. Lesson #4