ECE 260B – CSE 241A Testing 1http://vlsicad.ucsd.edu ECE260B – CSE241A Winter 2005 Testing Website:

ECE 260B – CSE 241A Testing 2http://vlsicad.ucsd.edu Outline  Defects and Faults  ATPG for Combinational Circuits  ATPG for Sequential Circuits

ECE 260B – CSE 241A Testing 3http://vlsicad.ucsd.edu Fault models

ECE 260B – CSE 241A Testing 4http://vlsicad.ucsd.edu Fault Models Most Popular - “Stuck - at” model  : x1 sa1  : x1 sa0 or x2 sa0 Covers many other occurring faults, such as opens and shorts.

ECE 260B – CSE 241A Testing 5http://vlsicad.ucsd.edu Fault Models  To detect an and-bridging  Detect a s-a-0 and b = 0  Detect b s-a-0 and a = 0  To detect a transition fault  Pattern 1: c = 1  Pattern 2: detect c s-a-1 c a b good bad and 1

ECE 260B – CSE 241A Testing 6http://vlsicad.ucsd.edu Problem with stuck-at model: CMOS open fault Sequential effect Needs two vectors to ensure detection! Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive!

ECE 260B – CSE 241A Testing 7http://vlsicad.ucsd.edu Problem with stuck-at model: CMOS short fault Causes short circuit between Vdd and GND for A=C=0, B=1 Possible approach: Supply Current Measurement (IDDQ) but: not applicable for gigascale integration

ECE 260B – CSE 241A Testing 8http://vlsicad.ucsd.edu Exhaustive Algorithm  For n-input circuit, generate all 2 n input patterns  Infeasible, unless circuit is partitioned into cones of logic, with < 15 inputs l Perform exhaustive ATPG for each cone l Misses faults that require specific activation patterns for multiple cones to be tested 

ECE 260B – CSE 241A Testing 9http://vlsicad.ucsd.edu  Flow chart for method  Use to get tests for 60-80% of faults, then switch to D- algorithm or other ATPG for rest Random Pattern Generation

ECE 260B – CSE 241A Testing 10http://vlsicad.ucsd.edu Fault simulation

ECE 260B – CSE 241A Testing 11http://vlsicad.ucsd.edu g = G (X 1, X 2, …, X n ) for the fault site f j = F j (g, X 1, X 2, …, X n ) 1 j m X i = 0 or 1 for 1 i n      Boolean Difference Symbolic Method (Sellers et al.)

ECE 260B – CSE 241A Testing 12http://vlsicad.ucsd.edu  Shannon’s Expansion Theorem: F (X 1, X 2, …, X n ) = X 2 F (X 1, 1, …, X n ) + X 2 F (X 1, 0, …, X n )  Boolean Difference (partial derivative): F j g  Fault Detection Requirements (for g s-a-0): G (X 1, X 2, …, X n ) = 1 F j g = F j (1, X 1, X 2, …, X n ) F j (0, X 1, …, X n ) = F j (1, X 1, X 2, …, X n ) F j (0, X 1, …, X n ) = 1         Boolean Difference (Sellers, Hsiao, Bearnson)

ECE 260B – CSE 241A Testing 13http://vlsicad.ucsd.edu Basic Terms, Path Sensitization Techniques Used: D-algorithm, Podem Goals: Determine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) sa Fault propagation Fault enabling  Controllability: the ease of controlling the state of a node in the circuit  Observability: the ease of observing the state of a node in the circuit

ECE 260B – CSE 241A Testing 14http://vlsicad.ucsd.edu 5-Value Logic  0 – binary 0 in both good and fault circuit  1- binary 1 in both good and fault circuit  X – don’t care  D – binary 1 in good circuit, 0 in bad circuit  D – binary 0 in good circuit, 1 in bad circuit

ECE 260B – CSE 241A Testing 15http://vlsicad.ucsd.edu Primitive D-Cube of Failure  Models circuit faults: l Stuck-at-0 l Stuck-at-1 l Bridging fault (short circuit) l Arbitrary change in logic function  AND Output sa0: “1 1 D”  AND Output sa1: “0 X D ” “X 0 D ”  Wire sa0: “D”  Propagation D-cube – models conditions under which fault effect propagates through gate

ECE 260B – CSE 241A Testing 16http://vlsicad.ucsd.edu Forward Implication  Results in logic gate inputs that are significantly labeled so that output is uniquely determined  AND gate forward implication table:

ECE 260B – CSE 241A Testing 17http://vlsicad.ucsd.edu Backward Implication  Unique determination of all gate inputs when the gate output and some of the inputs are given

ECE 260B – CSE 241A Testing 18http://vlsicad.ucsd.edu 1 Fault Sensitization 2 Fault Propagation 3 Line Justification Path Sensitization Method Circuit Example

ECE 260B – CSE 241A Testing 19http://vlsicad.ucsd.edu  Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 0 D D D D D Path Sensitization Method Circuit Example

ECE 260B – CSE 241A Testing 20http://vlsicad.ucsd.edu  Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D D D D Path Sensitization Method Circuit Example

ECE 260B – CSE 241A Testing 21http://vlsicad.ucsd.edu  Final try: path g – i – j – k – L – test found! 0 D D D 1 D D Path Sensitization Method Circuit Example

ECE 260B – CSE 241A Testing 22http://vlsicad.ucsd.edu D-Algorithm – Top Level 1.Number all circuit lines in increasing level order from PIs to POs; 2.Select a primitive D-cube of the fault to be the test cube; 3. D-drive (); 4. Consistency (); 5.return ();

ECE 260B – CSE 241A Testing 23http://vlsicad.ucsd.edu D-Algorithm – Propagation  D-frontier: all gates whose output is X, at least one input is D or D  J-frontier: all gates whose output is defined, but is not implied by the input values

ECE 260B – CSE 241A Testing 24http://vlsicad.ucsd.edu  Step 1 – D-Drive – Set A = 1 D 1 D Example 7.2: Fault A sa0

ECE 260B – CSE 241A Testing 25http://vlsicad.ucsd.edu D 1 0 D  Step 2 – D-Drive – Set f = 0 D Step 2 -- Example 7.2

ECE 260B – CSE 241A Testing 26http://vlsicad.ucsd.edu D 1 0 D  Step 3 – D-Drive – Set k = 1 D 1 D Step 3 -- Example 7.2

ECE 260B – CSE 241A Testing 27http://vlsicad.ucsd.edu D 1 0 D  Step 4 – Consistency – Set g = 1 D 1 D 1 Step 4 -- Example 7.2

ECE 260B – CSE 241A Testing 28http://vlsicad.ucsd.edu D 1 0 D  Step 5 – Consistency – f = 0 Already set D 1 D 1 Step 5 -- Example 7.2

ECE 260B – CSE 241A Testing 29http://vlsicad.ucsd.edu D 1 0 D  Step 6 – Consistency – Set c = 0, Set e = 0 D 1 D Step 6 -- Example 7.2

ECE 260B – CSE 241A Testing 30http://vlsicad.ucsd.edu D 1 0 X D  Step 7 – Consistency – Set B = 0  D-Chain dies D 1 D n Test cube: A, B, C, D, e, f, g, h, k, L D-Chain Dies -- Example 7.2

ECE 260B – CSE 241A Testing 31http://vlsicad.ucsd.edu Example 7.3 – Fault s sa1  Primitive D-cube of Failure 1 D sa1

ECE 260B – CSE 241A Testing 32http://vlsicad.ucsd.edu Example 7.3 – Step 2 s sa1  Propagation D-cube for v 1 D 0 sa1 D 1 D

ECE 260B – CSE 241A Testing 33http://vlsicad.ucsd.edu Example 7.3 – Step 2 s sa1  Forward & Backward Implications 1 D sa1 0 D D

ECE 260B – CSE 241A Testing 34http://vlsicad.ucsd.edu Example 7.3 – Step 3 s sa1  Propagation D-cube for Z – test found! 1 D sa1 0 D D D

ECE 260B – CSE 241A Testing 35http://vlsicad.ucsd.edu PODEM High-Level Flow 1. Assign binary value to unassigned PI 2. Determine implications of all PIs 3. Test Generated? If so, done. 4. Test possible with more assigned PIs? If maybe, go to Step 1 5. Is there untried combination of values on assigned PIs? If not, exit: untestable fault 6. Set untried combination of values on assigned PIs using objectives and backtrace. Then, go to Step 2

ECE 260B – CSE 241A Testing 36http://vlsicad.ucsd.edu  Select path s – Y for fault propagation sa1 Example Step 1 s sa1

ECE 260B – CSE 241A Testing 37http://vlsicad.ucsd.edu  Initial objective: Set r to 1 to sensitize fault 1 sa1 Example Step 2 s sa1

ECE 260B – CSE 241A Testing 38http://vlsicad.ucsd.edu Example Step 3 s sa1  Backtrace from r 1 sa1

ECE 260B – CSE 241A Testing 39http://vlsicad.ucsd.edu Example Step 4 s sa1  Set A = 0 in implication stack 1 0 sa1

ECE 260B – CSE 241A Testing 40http://vlsicad.ucsd.edu Example Step 5 s sa1  Forward implications: d = 0, X = 1 1 sa

ECE 260B – CSE 241A Testing 41http://vlsicad.ucsd.edu Example Step 6 s sa1  Initial objective: set r to 1 1 sa

ECE 260B – CSE 241A Testing 42http://vlsicad.ucsd.edu Example Step 7 s sa1  Backtrace from r again 1 sa

ECE 260B – CSE 241A Testing 43http://vlsicad.ucsd.edu Example Step 8 s sa1  Set B to 1. Implications in stack: A = 0, B = 1 1 sa

ECE 260B – CSE 241A Testing 44http://vlsicad.ucsd.edu D Example Step 9 s sa1  Forward implications: k = 1, m = 0, r = 1, q = 1, Y = 1, s = D, u = D, v = D, Z = 1 1 sa D D

ECE 260B – CSE 241A Testing 45http://vlsicad.ucsd.edu Backtrack -- Step 10 s sa1  X-PATH-CHECK shows paths s – Y and s – u – v – Z blocked (D-frontier disappeared) 1 sa

ECE 260B – CSE 241A Testing 46http://vlsicad.ucsd.edu Step s sa1  Set B = 0 (alternate assignment) 1 sa1 0 0

ECE 260B – CSE 241A Testing 47http://vlsicad.ucsd.edu Backtrack -- s sa1 1 sa  Forward implications: d = 0, X = 1, m = 1, r = 0, s = 1, q = 0, Y = 1, v = 0, Z = 1. Fault not sensitized

ECE 260B – CSE 241A Testing 48http://vlsicad.ucsd.edu Step s sa1  Set A = 1 (alternate assignment) 1 sa1 1

ECE 260B – CSE 241A Testing 49http://vlsicad.ucsd.edu Step s sa1  Backtrace from r again 1 sa1 1

ECE 260B – CSE 241A Testing 50http://vlsicad.ucsd.edu Step s sa1  Set B = 0. Implications in stack: A = 1, B = 0 1 sa1 1 0

ECE 260B – CSE 241A Testing 51http://vlsicad.ucsd.edu Backtrack -- s sa1  Forward implications: d = 0, X = 1, m = 1, r = 0. Conflict: fault not sensitized. Backtrack sa

ECE 260B – CSE 241A Testing 52http://vlsicad.ucsd.edu Step s sa1  Set B = 1 (alternate assignment) 1 sa1 1 1

ECE 260B – CSE 241A Testing 53http://vlsicad.ucsd.edu Fault Tested -- Step 18 s sa1  Forward implications: d = 1, m = 1, r = 1, q = 0, s = D, v = D, X = 0, Y = D 1 sa D 0 D D X D

ECE 260B – CSE 241A Testing 54http://vlsicad.ucsd.edu Comparison  Path sensitization: multiply SAT problems  D-algorithm: decisions are made at the J-frontier  PODEM: decisions are made at the PIs  FAN: l Multiply paths are traced back simultaneously l A decision can be made at a headline

ECE 260B – CSE 241A Testing 55http://vlsicad.ucsd.edu Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) Year History of Algorithm Speedups

ECE 260B – CSE 241A Testing 56http://vlsicad.ucsd.edu Sequential Circuits: State!  Combinational circuit testing is relatively easy  Sequential circuit testing needs to drive sequential elements to specific state to test a fault

ECE 260B – CSE 241A Testing 57http://vlsicad.ucsd.edu Sequential Circuit Controllability and Observability

ECE 260B – CSE 241A Testing 58http://vlsicad.ucsd.edu Ad-hoc Test Inserting multiplexer improves testability

ECE 260B – CSE 241A Testing 59http://vlsicad.ucsd.edu Scan-based Test

ECE 260B – CSE 241A Testing 60http://vlsicad.ucsd.edu Scan-based Test —Operation

ECE 260B – CSE 241A Testing 61http://vlsicad.ucsd.edu Scan-Path Testing Partial-Scan can be more effective for pipelined datapaths

ECE 260B – CSE 241A Testing 62http://vlsicad.ucsd.edu Boundary Scan (JTAG) Board testing becomes as problematic as chip testing

ECE 260B – CSE 241A Testing 63http://vlsicad.ucsd.edu Self-test Rapidly becoming more important with increasing chip-complexity and larger modules

ECE 260B – CSE 241A Testing 64http://vlsicad.ucsd.edu Design verification testing

ECE 260B – CSE 241A Testing 65http://vlsicad.ucsd.edu Production testing

ECE 260B – CSE 241A Testing 66http://vlsicad.ucsd.edu Cost of finding failing chip

ECE 260B – CSE 241A Testing 67http://vlsicad.ucsd.edu Thanks