IEEE’s Hands on Practical Electronics (HOPE) Lesson 8: Transistors.

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IEEE’s Hands on Practical Electronics (HOPE)

Presentation transcript:

IEEE’s Hands on Practical Electronics (HOPE) Lesson 8: Transistors

Last Week Transistors –Metal Oxide Semiconductor Field Effect Transistor –Drain, Body, Source, Gate –Function as an electronic switch NMOS –Gate voltage higher than source => current ON –Gate voltage lower than source => current OFF

This Week PMOS Transistors Review: NMOS Transistors PMOS Operation Lab

PMOS For a PMOS, whichever terminal is biased at a higher potential (voltage) is called the source, the other is called the drain. G D S B

PMOS Fabrication will be discussed in a later lesson. Today, we’ll explain how PMOS transistors work. G D S B

PMOS We saw this last week for NMOS. For a PMOS, N- type regions become P-type regions and vice versa.

PMOS To turn on a PMOS, apply a voltage to the gate that is lower than the source voltage.

PMOS A gate voltage higher than the source will not turn on the PMOS

Review: NMOS Transistor Remember these pictures from last week?

Review: NMOS Transistor With too LOW of a gate voltage, electrons cannot get through. No current flows. N type P type No current

Review: NMOS Transistor Apply a voltage to make the p-type material behave like n-type. Current flows. N type Current

Review: NMOS Transistor Gate voltage LOWER than source voltage N type P type

Review: NMOS Transistor Gate voltage HIGHER than source voltage N type Current

PMOS Transistor With too HIGH a gate voltage, holes cannot get through: no current. P type N type No current

PMOS Transistor Apply a voltage to make the n-type material behave like p-type P type Current

PMOS Transistor Gate voltage HIGHER than source voltage P type N type No current

PMOS Transistor Gate voltage LOWER than source voltage P type Current

Summary You are given two different voltages (HIGH & LOW). Applying the two voltages to the terminals of a MOSFET and one of the two voltages to the gate, the following combinations are possible: TypeGate Voltage Current? PMOSHIGHOFF PMOSLOWON NMOSHIGHON NMOSLOWOFF

Sample Circuit This is a graph of I d versus V in V DD R D + v DS – i D V DD R D + v DS – i D

Drain current This graph is an approximate graph of the drain current. The first portion behaves like a parabola. Then it flattens, and increasing the voltage does not increase the current. This is “saturation.”

Digital Logic Digital Logic only concerns itself with ON or OFF ON can be considered to be above some value, and OFF can be considered to be below that value.

Lab PMOS transistor is OFF Current does not flow LED is OFF

Lab PMOS transistor is ON Current flows LED is ON

Lab Be sure to connect all the wires – ask for help if you need it.

Lab Unplug the wire from the gate to 9V and plug that wire into ground. Do not just leave it “floating”!

Lab How does the circuit from last week compare to the circuit from this week?

Lab