Lecture 9: Sequential Networks: Implementation CSE 140: Components and Design Techniques for Digital Systems Fall 2014 CK Cheng Dept. of Computer Science and Engineering University of California, San Diego 1

Implementation Format and Tool Procedure Excitation Tables Example 2

3 Mealy Machine: y i (t) = f i (X(t), S(t)) Moore Machine: y i (t) = f i (S(t)) s i (t+1) = g i (X(t), S(t)) C1C2 CLK x(t) y(t) Mealy Machine C1C2 CLK x(t) y(t) Moore Machine S(t) Canonical Form: Mealy and Moore Machines

D iClicker 4 y CLK x Q In the logic diagram below, a D flip-flop has input x and output y. A: x= Q(t), y=Q(t) B: x=Q(t+1), y=Q(t) C: x=Q(t), y=Q(t+1) D: None of the above

Understanding Current State and Next State in a sequential circuit 5 today sunrise Preparing for tomorrow according to our effort in today

C1C2 CLK x(t) y(t) Implementation Format Q(t) Q(t+1) = h(x(t), Q(t)) Circuit C1 y(t) = f(x(t), Q(t)) Circuit C2 6 Canonical Form: Mealy & Moore machines State Table  Netlist Tool: Excitation Table

Implementation Tool: Excitation Table 7 x(t) Q(t) CLK C1 idx(t)Q(t)Q(t+1) State Table Find D, T, (S R), (J K) to drive F-Fs

Implementation Tool: Excitation Table 8 x(t) Q(t) CLK Q(t) C1 idx(t)Q(t)T(t)Q(t+1) idx(t)Q(t)Q(t+1) State Table Excitation Table Example with T flip flop T(t)

Implementation Tool: Excitation Table 9 x(t) Q(t) CLK Q(t) C1 idx(t)Q(t)T(t)Q(t+1) Excitation Table Implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t))

Implementation: Procedure State Table => Excitation Table Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)). 10

Implementation: Procedure State Table => Excitation Table Problem: Given a state table, we have NS: Q(t+1) = h(x(t),Q(t)) We find D, T, (S R), (J K) to drive F-Fs from Q(t) to Q(t+1). Excitation Table: The setting of D(t), T(t), (S(t) R(t)), (J(t) K(t)) to drive Q(t) to Q(t+1). We implement combinational logic C1 D(t), T(t), (S(t) R(t)), (J(t) K(t)) are functions of (x,Q(t)). 11

Implementation: Procedure F-F State Table F-F Excitation Table 12 DTSRJK PS Q(t) NS Q(t+1) PS Q(t) DTSRJK D F-F D(t)= e D (Q(t+1), Q(t)) T F-F T(t)= e T (Q(t+1), Q(t)) SR F-F S(t)= e S (Q(t+1), Q(t)) R(t)= e R (Q(t+1), Q(t)) JK F-F J(t)= e J (Q(t+1), Q(t)) K(t)= e K (Q(t+1), Q(t))

State table of JK F-F: Q(t) Q(t+1) JK Excitation table of JK F-F : PS NS Q(t) Q(t+1) JK If Q(t) is 1, and Q(t+1) is 0, then JK needs to be -1. Excitation Table 13

Excitation Tables and State Tables PS NS Q(t) Q(t+1) SR Excitation Tables: PS NS Q(t) Q(t+1) T PS SR Q(t) Q(t+1) SR PS T Q(t) Q(t+1) T State Tables: 14

PS NS Q(t) Q(t+1) JK Excitation Tables: PS NS Q(t) Q(t+1) D PS JK Q(t) Q(t+1) JK PS D Q(t) Q(t+1) D State Tables: Excitation Tables and State Tables 15

Implementation: Procedure 1.State table: y(t)= f(Q(t), x(t)), Q(t+1)= h(x(t),Q(t)) 2.Excitation table of F-Fs: D(t)= e D (Q(t+1), Q(t)); T(t)= e T (Q(t+1), Q(t)); (S, R), or (J, K) 3.From 1 & 2, we derive excitation table of the system D(t)= g D (x(t),Q(t))= e D (h(x(t),Q(t)),Q(t)); T(t)= g T (x(t),Q(t))= e T (h(x(t),Q(t)),Q(t)); (S, R) or (J, K). 4.Use K-map to derive optional combinational logic implementation. D(t)= g D (x(t),Q(t)) T(t)= g T (x(t),Q(t)) y(t)= f(x(t),Q(t)) 16

Implementation: Example Implement a JK F-F with a T F-F PS JK Q(t) Q(t+1) = h(J(t),K(t),Q(t)) = J(t)Q’(t)+K’(t)Q(t) JK Implement a JK F-F: Q Q’ C1 J K T 17 Q

id J(t) 0 1 K(t) Q(t) Q(t+1) T(t) PS NS Q(t) Q(t+1) Excitation Table of T Flip-Flop T(t) = Q(t) ⊕ Q(t+1) T(t) = Q(t) XOR ( J(t)Q’(t) + K’(t)Q(t)) Excitation Table of the Design Example: Implement a JK flip-flop using a T flip-flop T 18

Q(t) J K T(J,K,Q): T = K(t)Q(t) + J(t)Q’(t) Q Q’ J K T Example: Implement a JK flip-flop using a T flip-flop 19

iClicker 20 Given a flip-flop, the relation of its state table and excitation table is A.One to one B.One to many C.Many to one D.Many to many E.None of the above

21 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 PS Next state S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3

22 Let’s implement our free running 2-bit counter using T-flip flops S0S1S2S3S0S1S2S3 S1S2S3S0S1S2S3S0 State Table S0S0 S0S0 S1S1 S1S1 S2S2 S2S2 S3S3 S3S3 State Table with Assigned Encoding Current Next

23 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table

24 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table

25 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table T 0 (t) = T 1 (t) = Q 0 (t+1) = T 0 (t) Q’ 0 (t)+T’ 0 (t)Q 0 (t) Q 1 (t+1) = T 1 (t) Q’ 1 (t)+T’ 1 (t)Q 1 (t)

26 Let’s implement our free running 2-bit counter using T-flip flops idQ 1 (t)Q 0 (t)T 1 (t)T 0 (t)Q 1 (t+1)Q 0 (t+1) Excitation table T 0 (t) = 1 T 1 (t) = Q 0 (t)

27 T Q Q’ T Q Q0Q0 Q1Q1 1 T1T1 Free running counter with T flip flops T 0 (t) = 1 T 1 (t) = Q 0 (t)

28 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. Assign mapping a:0, b:1

29 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. Assign mapping a:0, b:1 PI Q How many states should the pattern recognizer have A.One because it has one output B.One because it has one input C.Two because the input can be one of two states (a or b) D.Three because E.Four because.....

30 PI Q: How many states should the pattern recognizer have A.One because it has one output B.One because it has one input C.Two because the input can be one of two states (a or b) D.Three because E.Four because.....

31 Implementation: State Diagram => State Table => Netlist Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0. S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0

32 State Diagram => State Table with State Assignment State Assignment S0: 00 S1: 01 S2: 10 PS\xab S0S1,0S0,0 S1S2,0S0,0 S2S2,0S0,1 PS\x ,000,0 0110,000,0 1010,000,1 Q 1 (t+1)Q 0 (t+1), y a: 0 b: 1 S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0

33 Example 2: State Diagram => State Table => Excitation Table => Netlist PS\x ,000,0 0110,000,0 1010,000,1 idQ1Q0xQ1Q0xD1D0D1D0 y

x(t) Q1Q Q0Q0 D 1 (t): D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x idQ1Q0xQ1Q0xD1D0D1D0 y Example 2: State Diagram => State Table => Excitation Table => Netlist

35 D Q Q’ D Q Q1Q1 Q0Q0 D1D1 D0D0 Q0Q0 Q1Q1 x’ D 1 (t) = x’Q 0 + x’Q 1 D 0 (t)= Q’ 1 Q’ 0 x’ y= Q 1 x x y Q’ 1 Q’ 0 x’ Example 2: State Diagram => State Table => Excitation Table => Netlist

36 D Q Q’ D Q Q1Q1 Q0Q0 D1D1 D0D0 Q0Q0 Q1Q1 x’ x y Q’ 1 Q’ 0 x’ Example 3: State Diagram => State Table => Excitation Table => Netlist S1 S0 a/0 b/0 a/0 b/1 S2 a/0 b/0 iClicker: The relation between the above state diagram and sequential circuit. A.One to one. B.One to many C.Many to one D.Many to many E.None of the above

Modified 2 bit counter 37 Q 0 (t) Q 1 (t) D Q Q’ D Q CLK x(t) Q 0 (t) Q 1 (t) y(t)

Modified 2 bit counter 38 Q 0 (t) Q 1 (t) D Q Q’ D Q CLK x(t) Q 0 (t) Q 1 (t) y(t) y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t))

39 State table PS input x=0 x=1 Q 1 (t) Q 0 (t) | (Q 1 (t+1) Q 0 (t+1), y(t)) Present State | Next State, Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 Netlist  State Table  State Diagram  Input Output Relation State Assignment Characteristic Expression: y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t))

40 State table PS input x=0 x=1 01, 0 00, 0 10, 0 00, 0 11, 0 00, 0 00, 1 Q 1 (t) Q 0 (t) | Q 1 (t+1) Q 0 (t+1), y(t) Present State | Next State, Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1 Let: S 0 = 00 S 1 = 01 S 2 = 10 S 3 = 11 Remake the state table using symbols instead of binary code, e.g. ’00’ Netlist  State Table  State Diagram  Input Output Relation State Assignment y(t) = Q 1 (t)Q 0 (t) Q 0 (t+1) = D 0 (t) = x(t)’ Q 0 (t)’ Q 1 (t+1) = D 1 (t) = x(t)’(Q 0 (t) + Q 1 (t))

41 Netlist  State Table  State Diagram  Input Output Relation Given inputs and initial state, derive output sequence S1S1 S2S2 S3S3 S0S0 Time Input StateS0 Output S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1

42 Netlist  State Table  State Diagram  Input Output Relation Example: Given inputs and initial state, derive output sequence Time Input StateS0S1S0S1S2S3 Output (0 or 1)/1 S0S1S2S3S0S1S2S3 PS input x=0 x=1 S 1, 0 S 0, 0 S 2, 0 S 0, 0 S 3, 0 S 0, 0 S 0, 1 x/y S1S1 S2S2 S3S3 S0S0 0/0 1/0

43 Finite State Machine Example Traffic light controller –Traffic sensors: T A, T B (TRUE when there’s traffic) –Lights: L A, L B

44 FSM Black Box Inputs: CLK, Reset, T A, T B Outputs: L A, L B

45 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

46 FSM State Transition Diagram Moore FSM: outputs labeled in each state States: Circles Transitions: Arcs

47 FSM State Transition Table PSInputsNS TATA TBTB S00XS1 S01X S1XXS2 X0S3 S2X1 S3XXS0

48 State Transition Table PSInputsNS Q 1 (t)Q 0 (t)TATA TBTB Q 1 (t +1)Q 0 (t +1) 000X01 001X00 01XX10 10X011 10X110 11XX00 StateEncoding S000 S101 S210 S311 Q 1 (t+1)= Q 1 (t)  Q 0 (t) Q 0 (t+1)= Q’ 1 (t)Q’ 0 (t)T’ A + Q 1 (t)Q’ 0 (t)T’ B

49 FSM Output Table PSOutputs Q1Q1 Q0Q0 LA1LA1 LA0LA0 LB1LB1 LB0LB OutputEncoding green00 yellow01 red10 L A1 = Q 1 L A0 = Q’ 1 Q 0 L B1 = Q’ 1 L B0 = Q 1 Q 0

50 FSM Schematic: State Register

51 Logic Diagram

52 FSM Schematic: Output Logic

Summary: Implementation 53 Set up canonical form Mealy or Moore machine Identify the next states state diagram ⇨ state table state assignment Derive excitation table Inputs of flip flops Design the combinational logic don’t care set utilization