© BYU 13 COUNTERS Page 1 ECEn 224 COUNTERS Counters Transition Tables Moore Outputs Counter Timing

© BYU 13 COUNTERS Page 2 ECEn 224 General Sequential Systems D Q Current State State Memory Input Forming Logic Next State

© BYU 13 COUNTERS Page 3 ECEn 224 A Sequential Counter CLK Next State Current State The current state loads the next state values in response to the clock edge. IFL reacts after some gate delays to produce a new next state. Clock edges… D Q Current State State Memory +1 Next State 2 Master Slave

© BYU 13 COUNTERS Page 4 ECEn 224 Transition Table for 2-Bit Counter It is the truth table for the input forming logic… It describes what the next state values are as a function of the current state (clock is assumed)

© BYU 13 COUNTERS Page 5 ECEn 224 Implementation of 2-Bit Counter Q0 Q1 D Q CLK N1 N0 N0 = Q0’ N1 =Q1  Q0

© BYU 13 COUNTERS Page 6 ECEn 224 Example 2 – A Gray Code Counter N1= Q0 N0 = Q1’ Q1 D Q Q0 CLK N1 N0

© BYU 13 COUNTERS Page 7 ECEn 224 Example 3 – Not All Count Values Used Desired count sequence = 00 – 01 – … What should next state for 10 be?

© BYU 13 COUNTERS Page 8 ECEn 224 Example 3 – Not All Count Values Used Do the normal K-map minimization with don’t cares N1 = Q0Q1’N0 = Q0’

© BYU 13 COUNTERS Page 9 ECEn 224 Example 4 – A Ring Counter Desired count sequence = 001 – 010 – …

© BYU 13 COUNTERS Page 10 ECEn 224 Example 4 – A Ring Counter Desired count sequence = 001 – 010 – … Doing KMaps leads to: N2 = Q1 N1 = Q0 N0 = Q2 Q2Q2 Q1Q0Q1Q X 01X 11XX 101X Q2Q2 Q1Q0Q1Q X 011X 11XX 10X Q2Q2 Q1Q0Q1Q X1 01X 11XX 10X N2N1N0

© BYU 13 COUNTERS Page 11 ECEn 224 Example 4 – A Ring Counter D Q Q0 Q2 Q1 CLK

© BYU Initial State When a sequential circuit is powered on, we have no guarantee it will start in any particular state We must make sure our counters don’t start in an invalid state –They could remain stuck in invalid states! Most digital systems have a reset signal that is asserted after power up Designers must use flip flops with reset/set inputs as needed to achieve desired startup behavior 13 COUNTERS Page 12 ECEn 224

© BYU 13 COUNTERS Page 13 ECEn 224 A Ring Counter with Reset D Q SET D Q RST D Q RST Q0 Q2 Q1 CLK RESET Reset causes circuit to start in state “001”

© BYU 13 COUNTERS Page 14 ECEn 224 General Counter Design Procedure Write transition table for counter –Use X’s as appropriate Reduce each NX variable to a minimized equation Implement input forming logic (IFL) using gates Draw schematic using FF’s + IFL

© BYU 13 COUNTERS Page 15 ECEn 224 Counters With Alternative FF’s Current State Input Forming Logic T Inputs State Memory T Q

© BYU 13 COUNTERS Page 16 ECEn 224 Excitation Table for T Flip Flop Rearranging rows and/or columns… Tells how inputs affect outputTells what input is needed to achieve desired output transition In the end, they are the same table, just rearranged… Transition TableExcitation Table

© BYU 13 COUNTERS Page 17 ECEn 224 TFF Counter Design Using Augmented Transition Table Next state values Inputs to apply to achieve desired next state

© BYU 13 COUNTERS Page 18 ECEn 224 TFF Counter Design Using Augmented Transition Table Next state values Inputs to apply to achieve desired next state T2 = Q1Q0 T1 = Q0 T0 = ‘1’ Q2Q2 Q1Q0Q1Q T2

© BYU 13 COUNTERS Page 19 ECEn 224 TFF Counter Design ‘1’ CLK Q1 CLK T Q CLK Q2 Q0

© BYU 13 COUNTERS Page 20 ECEn 224 Excitation Table for JK Flip Flop Rearranging rows and/or columns… Tells how inputs affect output Tells what inputs to apply to achieve desired output transition Do you see why the X’s? In the end, they are the same table, just rearranged…

© BYU 13 COUNTERS Page 21 ECEn 224 JKFF Gray Code Counter Design Next state valuesInputs to apply to achieve desired next state

© BYU 13 COUNTERS Page 22 ECEn 224 JKFF Gray Code Counter Design Next state valuesInputs to apply to achieve desired next state J2 = Q1Q0’ K2 = Q1’ Q0’ J1 = Q2’ Q0 K1 = Q2 Q0 J0 = Q2 Q1 + Q2’ Q1’ = K0’ K0 = Q2’ Q1 + Q2 Q1’ = Q2  Q1

© BYU 13 COUNTERS Page 23 ECEn 224 General Counter Design Procedure Write transition table for counter –Use X’s as appropriate –If not DFF’s, augment table Reduce each FF input variable to a minimized equation Implement IFL with gates Draw schematic using FF’s + IFL

© BYU 13 COUNTERS Page 24 ECEn 224 Counters With Outputs Outputs D Q Current State Input Forming Logic Next State State Memory Output Forming Logic Outputs = f (CurrentState)

© BYU 13 COUNTERS Page 25 ECEn 224 Counters With Outputs Z=1 when count={0,3,6} Z is called a Moore or static output. It is a function only of the current state.

© BYU 13 COUNTERS Page 26 ECEn 224 Combined Transition Table Current stateNext stateOutput Z = Q2’ Q1’ Q0’ + Q2’ Q1 Q0 + Q2 Q1 Q0’ (implement OFL with gates)

© BYU 13 COUNTERS Page 27 ECEn 224 D Q Q2 Q1 Q0 N2 N1 N0 Z Counter With A Moore Output IFL OFL CLK

© BYU 13 COUNTERS Page 28 ECEn 224 Counter Timing Characteristics Q0 Q1 D Q CLK N1 N0 T ClockPeriod >= t CLK-Q + t IFL + t setup CLK Next State (N’s) Current State (Q’s) t CLK-Q t IFL t setup T ClockPeriod

© BYU 13 COUNTERS Page 29 ECEn 224 Counter Timing Example t CLK  Q = 1ns t IFL = 7ns t setup = 2ns Recall the following: –T = Clock period –f = Clock frequency or rate –T = 1/f –f = 1/T T >= 1ns + 7ns + 2ns = 10 ns (10 x s) f <= 1/T = 100 MHz (100 x 10 6 Hz)

© BYU 13 COUNTERS Page 30 ECEn 224 Output Timings CLK Z Current State t CLK  Q t OFL t CLK  Q t OFL Moore outputs appear t CLK  Q + t OFL after the clock edge.

© BYU 13 COUNTERS Page 31 ECEn 224 Counters and Timing The count sequence affects the size of IFL The size of the IFL affects t IFL t IFL affects T ClockPeriod Choosing binary counts is not always fastest or smallest

© BYU 13 COUNTERS Page 32 ECEn 224 Example Problem Design a 3-bit binary counter The Z output is TRUE iff count value is even The Y output is TRUE iff count value is multiple of 3