1 COMP541 Sequential Circuits Montek Singh Feb 1, 2012

2Topics  Sequential Circuits Latches Latches Flip Flops Flip Flops  Verilog for sequential design Example: A simple counter Example: A simple counter

3 Sequential Circuits  State of system is info stored  That, and inputs, determine outputs

4 Types of Sequential Circuits  Synchronous State changes synchronized by one or more clocks State changes synchronized by one or more clocks  Asynchronous Timing of changes are independent of any clocks Timing of changes are independent of any clocks

5 Clocking of Synchronous  Changes enabled by clock

6Comparison  Synchronous Easier to analyze because can factor out gate delays Easier to analyze because can factor out gate delays Set clock so changes occur before next clock pulse Set clock so changes occur before next clock pulse  Asynchronous Potentially faster Potentially faster Harder to analyze (more subtle, but more powerful!) Harder to analyze (more subtle, but more powerful!)  Most of my research!  Will look mostly at synchronous

Storage Elements  Latch  Flip-Flop – a latch that transitions on a clock  Registers  Addressable memories or banks of registers 7

8 Basic Storage  Apply low or high for longer than t pd  Feedback will hold value

Bistable Circuit Analysis  Consider 2 possible cases: Q = 0: then Q’ = 1 and Q = 0 (consistent) Q = 0: then Q’ = 1 and Q = 0 (consistent) Q = 1: then Q’ = 0 and Q = 1 (consistent) Q = 1: then Q’ = 0 and Q = 1 (consistent)  Bistable circuit stores 1 bit of state in the state variable, Q (or Q’)  But there are no inputs to control the state

10 SR (set-reset) Latches  Basic storage made from gates S & R both 0 in “resting” state Have to keep both from 1 at same time

11Operation

12 Latch Latch  Similar – made from NANDs

SR Latch Summary  SR stands for Set/Reset Latch Stores one bit of state (Q) Stores one bit of state (Q)  Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R = 0, Q = 1) Set: Make the output 1 (S = 1, R = 0, Q = 1) Reset: Make the output 0 (S = 0, R = 1, Q = 0) Reset: Make the output 0 (S = 0, R = 1, Q = 0)  Behavior undefined/invalid when: S = R = 1 S = R = 1

14 Add Control Input  Gates when state can change  Is there latch w/ no illegal state?

15 D-type Latch  No illegal state

16 Transparency of latches  As long as C (the control ) is high, state can change This is called transparency This is called transparency  What’s problem with that?

17 Effects of Transparency  Output of latch may feed back May cause/allow further state changes May cause/allow further state changes Behavior depends on actual gate delays Behavior depends on actual gate delays  Want to change latch state only once Behavior should depend only on logical values Behavior should depend only on logical values

18 Solution to Transparency: Flip-Flops  Flip-Flops: Ensure output changes only once per clock cycle Ensure output changes only once per clock cycle  Two commonly-used types of flip-flops: Master-Slave Master-Slave  Use a sequence of two latches Edge-Triggered Edge-Triggered  Implementation very different from latches

19 1. Master-Slave Flip-Flop  Either Master or Slave is enabled, not both

20 Timing Diagram  Trace the behavior  Note illegal state  Is it transparent?

21 Have We Fixed the Problem?  Output no longer transparent Combinational circuit can use last values Combinational circuit can use last values New inputs appear at latches New inputs appear at latches Not sent to output until clock low Not sent to output until clock low  But changes at input of FF when clock high do trigger next state Is this a problem? Is this a problem?  As clock faster, more problems  Have to guarantee circuit settles while clock low

22 2. Edge-Triggered Flip-Flops  New state latched on clock transition Low-to-high or high-to-low Low-to-high or high-to-low  +ve edge-triggered, -ve edge-triggered  Also: dual-edge-triggered Changes when clock high are ignored Changes when clock high are ignored  Note: Master-Slave sometimes called pulse triggered

23 D-Type Edge-Triggered  Is this +ve or –ve edge-triggered?

24 Standard Symbols – Latches  Circle at input indicates negation

25 Symbols – Master-Slave  Inverted ‘L’ indicates postponed output  Circle indicates whether enable is positive or negative  JK: like an SR flip-flop, but: If J=K=1, output is toggled If J=K=1, output is toggled Can make a toggle flip-flop (T flip-flop) from a JK Can make a toggle flip-flop (T flip-flop) from a JK

26 Symbols – Edge-Triggered  Arrow indicates edge trigger

27 Direct Inputs  Use to force Set/Reset independent of clock Direct set or preset Direct set or preset Direct reset or clear Direct reset or clear  Often used for power-up reset

Registers

Counters  Increments on each clock edge  Used to cycle through numbers For example, 000, 001, 010, 011, 100, 101, 110, 111, 000, 001… 000, 001, 010, 011, 100, 101, 110, 111, 000, 001… Not necessarily binary Not necessarily binary  Example uses: Digital clock displays Digital clock displays Program counter Program counter

Verilog for Sequential  New Verilog to describe sequential circuits Can use latches and flip-flops from library in schematic capture or Verilog Can use latches and flip-flops from library in schematic capture or Verilog And connect them using wires And connect them using wires  But more productive to write higher-level Verilog description 30

Register Data Type  Like wire but value is retained over time  Often causes latch or FF to be synthesized  Examples reg state; reg [15:0] addr; 31

Always Block  Example ( sensitivity list ) statement; statement;  Sensitivity list determines what might affect statements Could think of it as “statement is run when one of values in sensitivity list changes value” Could think of it as “statement is run when one of values in sensitivity list changes value”  Example next 32

Synthesize a Flip-Flop module flop (C, D, Q); input C, D; input C, D; output Q; output Q; reg Q; reg Q; C) C) begin Q = D; Q = D; endendmodule 33 negedge also possible

Blocking Assignment  Equal sign indicates blocking statements initialbegin B = A; C = B; end  Result is that new contents of B are in C, so all have contents of A. 34

Non-Blocking Assignment  <= indicates non-blocking statements initialbegin B <= A; C <= B; end  All RHS evaluated first, then assigned  Result is that old contents of B are in C  This is what is normally synthesized!!! 35

This is Not Software!  Don’t assign to same reg in more than one always block The always blocks are concurrent The always blocks are concurrent Doesn’t make sense to set reg from two signals Doesn’t make sense to set reg from two signals  Assignments in always blocks should be non-blocking You usually don’t mean sequential execution You usually don’t mean sequential execution Can’t synthesize anyway! Can’t synthesize anyway! 36

Asynchronous Reset module dff_v(CLK, RESET, D, Q); input CLK, RESET, D; input CLK, RESET, D; output Q; output Q; reg Q; reg Q; CLK or posedge RESET) begin begin if (RESET) if (RESET) Q <= 0; else else Q <= D; Q <= D; end end endmodule endmodule 37

Synchronous Reset CLK) begin begin if (RESET) if (RESET) state <= 0; else else state <= D; state <= D; end end 38

Verilog for a Counter module counter(input clk, output [23:0] cnt ); ); reg [23:0] cnt; (posedge clk) cnt <= cnt + 1; endmodule 39

Simulation vs Synthesis  If you don’t initialize regs in your circuits, simulator will complain many values will be X many values will be X  Electronics will work OK each reg in actual circuit will “wake up” to a 0 or 1 value each reg in actual circuit will “wake up” to a 0 or 1 value 40

Verilog 2001 Syntax  Can initialize regs at declaration reg onebit = 1’b0; reg [3:0] fourbits = 4’b1011; reg [23:0] cnt = 0; 41

Topics  Today Looked at basic latches Looked at basic latches Flip-flops Flip-flops Verilog for sequential circuits Verilog for sequential circuits Simple counter Simple counter 42

Read  Textbook Ch for today Ch for next class Ch for next class 43

Next Time  State Machines  Verilog to describe state machines 44