Digital Logic of Computer Engineering KKU.1 Chapter 5 Sequential Systems Latches and Flip-flops Synchronous Counter Asynchronous Counter

Digital Logic of Computer Engineering KKU. 2 Introduction Up to now everything has been combinational – the output at any instant of time depends only on what inputs are at the time. Later on of this course: sequential systems – systems that have memory. Thus, the output will depend not only on the present input but also on the past history – what has happened earlier.

Digital Logic of Computer Engineering KKU. 3 Clock Signals Two versions of a clock signal are as below. In the first, the clock signal is 0 half of the time and 1 half of the time. In the second, it is 1 for a shorter part of the cycle. The period of the signal (T on the diagram) is the length of one cycle. The frequency is the inverse (1/T). T

Digital Logic of Computer Engineering KKU. 4 Conceptual View of a Sequential System

Digital Logic of Computer Engineering KKU. 5 Terminology State: what is stored in memory. State table: shows for each input combination and each state, what the output is and what the next state is – what is to be stored in memory after the next clock. State diagram (or state graph): a graphical representation of the state table.  (Finite) State Machine

Digital Logic of Computer Engineering KKU. 6 State Table and State Diagram qq*z x=0x=1x=0x=1 AAB00 BCB10 CAD00 DCC00 A D B C 0/0 0/11/0 0/0 1/0 X/0 State tableState diagram present state next state output input

Digital Logic of Computer Engineering KKU. 7 The next state is a function of the present state and the input. The output also depends on the present state (and on the input). It may change on a clock transition, but it may change where the input changes, as well. In state diagram, there must be one path from each state for each possible input combination.

Digital Logic of Computer Engineering KKU. 8 Moore vs. Mealy Models Moore model circuit (state-based)  the outputs depend on the present state of the system but not on the inputs. Mealy model circuit (input-based)  the outputs depend on the inputs as well as the present state of the system.

Digital Logic of Computer Engineering KKU. 9 Moore: A system with no input and three outputs, that represent a number from 0 to 7, such that the outputs cycle through the sequence and repeat on consecutive clock inputs. Mealy: A system with two inputs,X 1 and X 2, and three outputs, Z 1, Z 2 and Z 3, that represent a number from 0 to 7, such that the output counts up if X 1 =0 and down if X 1 =1 and recycles if X 2 =0 and saturates if X 2 =1. Thus, the following output sequences might be seen:

Digital Logic of Computer Engineering KKU. 10 X 1 =0 X 2 = X 1 =0 X 2 = X 1 =1 X 2 = X 1 =1 X 2 =

Digital Logic of Computer Engineering KKU. 11 Design Process of Sequential Systems Table 5.1 Page 338  State table  Timing trace  State table with binary states  Truth table  K-map  equations

Digital Logic of Computer Engineering KKU. 12 Design Process of Sequential Systems qq*z x=0x=1x=0x=1 AAB00 BCB10 CAD00 DCC00 clk x qAABBCDCDCDC z State table Timing trace

Digital Logic of Computer Engineering KKU. 13 Design Process of Sequential Systems q1q1 q 1 *q 2 *z x=0x=1x=0x= State assignment State table with binary states qq1q1 q2q2 A00 B01 C10 D 11

Digital Logic of Computer Engineering KKU. 14 Design Process of Sequential Systems xq1q1 q2q2 q1*q1*q2*q2*z State assignment Truth table for system design 11 x q2q2 11 q2’q2’q2’q2’ x’ q1q1 q1’q1’ q1q2x q1q2x

Digital Logic of Computer Engineering KKU. 15 Latches and Flip-flops A latch is a binary storage device, composed of two or more gates, with feedback. The latch can store either a 0 (Q = 0 and P = 1) or a 1 (Q = 1 and P = 0) The P output is just labelled

Digital Logic of Computer Engineering KKU. 16 Latches (cont.) Edge-triggered rising/leading edge-triggered falling/trailing edge-triggered Level-triggered high level-triggered low level-triggered

Digital Logic of Computer Engineering KKU. 17 Latches (cont.) Example: a latch constructed with 2 NORs. S P R Q The equations for this system: and Normal storage stage  both inputs inactive (S = R = 0). and

Digital Logic of Computer Engineering KKU. 18 Latches (cont.) S P R Q Case 1: If S=1 and R=0 Case 2: If S=0 and R=1 Case 3: Finally, the flip-flop is not operated with both S and R active (=1).

Digital Logic of Computer Engineering KKU. 19 Latches (cont.)  D flip-flops (Delay flip-flops)  SR flip-flops (Set/Reset flip-flops)  T flip-flops (Toggle flip-flops)  JK flip-flops

Digital Logic of Computer Engineering KKU. 20 D flip-flops Dqq* D D  q*=D

Digital Logic of Computer Engineering KKU. 21 D flip-flops (cont.)

Digital Logic of Computer Engineering KKU. 22 D flip-flops (cont.) Two D flip-flops

Digital Logic of Computer Engineering KKU. 23 D flip-flops (cont.) With Clear and Preset Dqq* 01XX1 Static 10XX0 Immediate 00XX- Not allowed Clocked (as before)

Digital Logic of Computer Engineering KKU. 24 D flip-flops + Clear and Preset (cont.)

Digital Logic of Computer Engineering KKU. 25 SR flip-flops SRqq* SR 00q SR  1 x1 q R x R’ 1 q’ SS’ SR q Not allowed

Digital Logic of Computer Engineering KKU. 26 SR flip-flops (cont.)

Digital Logic of Computer Engineering KKU. 27 T flip-flops Tqq* T 0q T  q*=T  q

Digital Logic of Computer Engineering KKU. 28 JK flip-flops JKqq* JK 00q JK  1 1 q K 1 K’ 1 q’ JJ’ JK q

Digital Logic of Computer Engineering KKU. 29 JK flip-flops (cont.)

Digital Logic of Computer Engineering KKU. 30 Analysis of Sequential Systems Figure 5.21 Page 342  Circuit  Equations  State table  Timing trace  Timing diagram  Equations A*,B*  State diagram

Digital Logic of Computer Engineering KKU. 31 Flip-flop Design Techniques xq1q1 q2q2 q1*q1*q2*q2*z From the truth table, it’s clear that We need to create the appropriate flip-flop design table to obtain a truth table for the flip-flop inputs. z=q 1 q 2 qq*Input(s) Main truth table D flip-flops JK flip-flops SR flip-flops T flip-flops next

Digital Logic of Computer Engineering KKU. 32 Design with D Flip-flop Dq* q D xq1q1 q2q2 D 1 =q 1 *D 2 =q 2 *  From the main truth table main truth table

Digital Logic of Computer Engineering KKU. 33 Design with D Flip-flop (cont.) x q1q x q1q

Digital Logic of Computer Engineering KKU. 34 Implementation using D Flip-flops back

Digital Logic of Computer Engineering KKU. 35 Design with JK Flip-flop JKq* 00q q JK 000X 011X 10X1 11X0 xq1q1 q2q2 q1*q1*q2*q2*J1J1 K1K1 J2J2 K2K X0X XX X10X 01110X1X X1X XX X01X 11110X0X0   From the main truth table main truth table

Digital Logic of Computer Engineering KKU. 36 Design with JK Flip-flop (cont.) x q1q XX 10 XX x q1q XX 01 XX x q1q XX 11 XX 10 1 x q1q XX XX J 1 K 1 J 2 K 2 back

Digital Logic of Computer Engineering KKU. 37 Design with SR Flip-flop SRq* 00q q SR 000X X0 xq1q1 q2q2 q1*q1*q2*q2*S1S1 R1R1 S2S2 R2R X0X X X X X X0X0   From the main truth table main truth table

Digital Logic of Computer Engineering KKU. 38 Design with SR Flip-flop (cont.) x q1q X 10 X x q1q XX 01 X x q1q X 10 1 x q1q X X J 1 K 1 J 2 K 2 back

Digital Logic of Computer Engineering KKU. 39 Design with T Flip-flop Tq* 0q 1 q T xq1q1 q2q2 q1*q1*q2*q2*T1T1 T2T  From the main truth table main truth table

Digital Logic of Computer Engineering KKU. 40 Design with T Flip-flop (cont.) x q1q x q1q back

Digital Logic of Computer Engineering KKU. 41 Quick method for JK Because Notice that when q=0 And when q=1

Digital Logic of Computer Engineering KKU. 42 Quick method for JK (cont.) state table to maps

Digital Logic of Computer Engineering KKU. 43 Quick method for JK (cont.)  First column of J 1 and K 1 Second column  of J 1 and K 1 Conventional qq*JK 000X 011X 10X1 11X0

Digital Logic of Computer Engineering KKU. 44 Quick method for JK (cont.) Computation of J 2 and K 2 Conventional

Digital Logic of Computer Engineering KKU. 45 Quick method for JK (cont.) Computation of J 1 and K 1 Quick method

Digital Logic of Computer Engineering KKU. 46 Design of Synchronous Counters Design a decimal or decade counter using JK flip-flops: DCBAD*C*B*A* xxxx …………………… 1111Xxxx 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, …

Digital Logic of Computer Engineering KKU. 47 Design of Synchronous Counters (cont.) DC BA X1 X 1XX XX DC BA 1X 1X 1XX 1XX DC BA X 11X XX 11XX DC BA 11X1 X XX 11XX D* C* B* A*

Digital Logic of Computer Engineering KKU. 48 DC BA X1 X 1XX XX DC BA XX XX 1XX XX DC BA XXX XXX1 XXXX XXXX D* JDJDJDJD KDKDKDKD From the main truth table of the D*main truth table of the D* Design of Synchronous Counters (cont.)

Digital Logic of Computer Engineering KKU. 49 Design of Synchronous Counters (cont.) DC BA 1X 1X 1XX 1XX DC BA XX XX 1XXX XXX DC BA XXX XXX X1XX XXX C* JCJCJCJC KCKCKCKC From the main truth table of the C*main truth table of the C*

Digital Logic of Computer Engineering KKU. 50 Design of Synchronous Counters (cont.) DC BA X 11X XX 11XX DC BA X 11X XXXX XXXX DC BA XXXX XXXX 11XX XX B* JBJBJBJB KBKBKBKB From the main truth table of the C*main truth table of the C*

Digital Logic of Computer Engineering KKU. 51 Design of Synchronous Counters (cont.) DC BA 11X1 X XX 11XX DC BA 11X1 XXXX XXXX 11XX DC BA XXXX 11X1 11XX XXXX A* JAJAJAJA KAKAKAKA From the main truth table of the A*main truth table of the A*

Digital Logic of Computer Engineering KKU. 52 Example: A Base-16 Counter DCBAD*C*B*A*remark 10 21 32 43 54 65 76 87 98 A9A ABAB BCBC CDCD DEDE EFEF F0F0

Digital Logic of Computer Engineering KKU. 53 Example: A Base-16 Counter (cont.) J D = K D = CBA DC BA DC BA J C = K C = BA

Digital Logic of Computer Engineering KKU. 54 Example: A Base-16 Counter (cont.) J B = K B = A DC BA DC BA J A = K A = 1

Digital Logic of Computer Engineering KKU. 55 Example: An Up/Down Counter XCBAC*B*A*remark 10 21 32 43 54 65 76 07 70 01 12 23 34 45 56 676 J A = K A = 1 J B = K B = xA + xA J C = K C = xBA + xBA

Digital Logic of Computer Engineering KKU. 56 Example: 0, 3, 2, 4, 1, 5, 7, and repeat q1q1 q2q2 q3q3 q1*q1*q2*q2*q3*q3*remark 30 51 42 23 14 757 110XXX 6X6X 070

Digital Logic of Computer Engineering KKU. 57 Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)

Digital Logic of Computer Engineering KKU. 58 Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)

Digital Logic of Computer Engineering KKU. 59 Design of Asynchronous Counters Page 350…. Figure 5.31(2-bit counter)&5.32(timing delay) Advantage:  Simplicity of the hardware  no combinational logic required Disadvantage:  Speed

Digital Logic of Computer Engineering KKU. 60 Derivation of State tables and State Diagrams Consider the problem: Another way of wording this same problem is A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times.

Digital Logic of Computer Engineering KKU. 61 A sample input/output trace is x z q 1 *q 2 *z q1q1 q2q2 x=0x=1x=0x= First approach: save the previous 2 inputs. Knowing them and the present input  output. Just discard the older input stored in memory and store the newer one plus the current input.

Digital Logic of Computer Engineering KKU. 62 Second approach: store in memory the number of consecutive 1’s as follows:  A  Anone, that is, the last input was 0  B  Bone  C  Ctwo or more q*z qx=0x=1x=0x=1 ABCABC AAAAAA BCCBCC A B C 0/0 1/0 no 1’s one 1 two or more 1’s 0/0 1/1 0/0 1/0

Digital Logic of Computer Engineering KKU. 63 The second approach requires only 3 states, whereas the first requires 4. Both, however, use 2 flip-flops. Consider: the system produces a 1 if the input has been 1 for 25 consecutive clock times. Now the first approach requires to store the last 24 inputs and a state table of 2 24 rows. The second approach requires 25 states which can be coded with 5 flip-flops.