System Overview of the Phase 1 Pixel Upgrade CMS Upgrade Workshop CERN 14. May 2009 R. Horisberger Paul Scherrer Institut

BPIX 3 Layer  4 Layers FPIX 2x2 Disk  3x2 Disk CO2 cooling based Ultra Light Mechanics Shift material budget out of tracking eta - region Modify PSI46 ROC for 160MHz digital readout & Increase depth of ROC buffers Serialized binary optical readout at 320 MHz to modified px-FED (new piggy cards) Rebuilt new AOH lasers  320MHz binary transmission Same FEC’s, identical TTC & ROC programming Use existing fibres & cables Keep LV-power supply & push more current through cables Pixel Upgrade Phase 1 (2014)

Current Pixel System with Supply Tubes / Cylinders FPIX service cylinder BPIX supply tube DOH & AOH mother board + AOH’s Power board endflange prints Layer 3 & 1+2

BPIX Cabling & flexible cooling pipes

Shift Material out of tracking Volume  new BPIX modules with long pigtails (~1.2m) (  micro-twisted pairs) FPIX service cylinder DOH & AOH mother board + AOH’s power board Move DOH & AOH boards back by 50-60cm

BPIX/FPIX Envelope Definition for 4 Layer Pixel System Various iterations forth and back by R.H. / Silvan Steuli / Kirk Arndt  no further changes since ! All barrel layers 4 module long  small eta hole of  ~ 0.08 at  =1.288

7 module geometries 168 modules per disk Total 4x1080 = 4320 ROC 72 outer & 44 inner radius modules 1 module geometry 116 modules per disk  1856 ROCs Total 6x1856 = 11’1136 ROC R mm R 58.7 mm R 161 mm R 39 mm FPIX Conceptual Layout Present FPIX 2x2 Disk 2014 FPIX 2x3 Disk

BPIX Upgrade Phase 1 (2013)  1216 modules (1.6 x present BPIX)

Each half shell has 10 cooling loops Each supply tube feeds 5 cooling loops Angle bend (~3 0 ) during insertion taken by carbon fibre hinge Stainless steel tubes diameter = 1.8mm wall thickness = 100μm Carbon fiber hinge Inertion of BPIX – Supplytube System with new CO2 Cooling New axis of rotation (~3 degrees) during pixel insertion

− 10 − Design Status BPIX Mechanics - April 2009Silvan Streuli PSI Villigen Prototype Fabrication Layer bar pressure tested Tubes, 50  wall thickness Weight Layer1 42g + 7g CO 2

− 11 − Design Status BPIX Mechanics - May 2009Silvan Streuli PSI Villigen Stainless steel facets used as heater resistors to simulate the power consumption of the sensor modules. Daisy chained connected (blue cable). Cooling tubes are electrically isolated to the stainless steel facets Thermal isolation material. Top lid not shown. Test of long CO2 cooling loop ( as in Layer 1)

px-AOH px-DOH PLL Delay25 px-FED px-FEC crt, 40MHz fast I 2 C 40 MHz analog out trk-FEC CCU I2CI2C I2CI2C CMS Pixel Read Out System 40MHz analog optical Current System: 0-suppressed analog coded data readout at 40MHz ABAB New Phase 1 System: 0-suppressed serial binary data readout at 320MHz, same data structure 320 MHz binary 320 MHz binary optical

Analog readout (40MHz) serial (1 or 2 channels) Double columns in ROC blocked until read out controlled by serial readout token: TBM-ROC1-…-16-TBM analog multiplexer and line-driver in TBM BPIX module 4 x 4 ROC  TBM  AOH  pxFED A - channel B - channel skip

ROC TBM analog summing amplifiers A fibre B fibre Current Pixel Module Readout Layer 1& 2  2 Fibre A & B Layer 3  1 Fibre A ROC  TBM : 40 MHz analog readout TBM  pxFED : 40 MHz analog readout 40 MHz

Pixel uses analog coded digital pixel readout Pixel address 5 x 3 bit Pulse height 1 x 8 bit  total 23 bits/ pixel hit in 6 clock cycles chip header 1 pixel hit ub b 3 rd c 1 c 2 r 1 r 2 r 3 ph  160 Mbits/sec link speed resp pJ/bit 8 levels = 3bits Present analog coded data transfer of pixel system

ROC TBM analog summing amplifiers New Serialized Binary Pixel Module Readout Layer  1 Fibre/module ROC  TBM : 160 MHz digital readout TBM  pxFED : 320 MHz digital readout 160 MHz 320 MHz

New serial binary data transfer of pixel system time 25ns 40 MHz LHC Clock 1111 XXXX pulse heightrow/column address 1 pixel hit 150nsec long 24 bits with 160 MHz ROC header 12 bit long New ROC serial bit clock is 160MHz  4 bits / LHC clock cycle 160 MHz clock to be generated in each ROC by 40 MHz  160 MHz PLL circuit  See talk H-C. Kästli

Pixel ROC 26 dcol 160 pix/each TBM-chip 4 x 4 ROC 160 MHz serial binary 320 MHz serial binary pxFED replace present ADC plug-in card with deserializer card deserializer plug in card New TBM purely digital chip no x-tra data buffering Multiplex 2 token passages Core of ROC chip unchanged but modified I/O periphery: 1) address DAC removed 2) 1 ADC for pulse height added 3) 40MHz  160MHz PLL added 160 MHz PLL 1x ADC (8-bit) 160/ 320 MHz PLL Changes for 160/320 MHz serial binary readout Changes

ADC PLL 40MHz Core of chip untouched ! Only changes to periphery column periphery Pixel cell Implications for the ROC Remove DAC Add PLL 40 MHz  160 MHz Add 160MHz bit serializer Replace analog driver with digital driver

Pixel FED HEPHY, Vienna M.Pernicka H. Steininger M. Friedl 3x 12 channels with 9 piggy-back ADC cards Replace ADC cards with new deserializer piggy-back cards

Opto-Rx Measurements for Pixel Upgrade M.Friedl, M.Pernicka HEPHY Vienna

Opto-Rx Measurements for Pixel Upgrade What? Why? How? Digital optical 320 Mb/s transmission is intended for pixel phase 1 upgrade Recycling of existing optical links possible? –Sender side appears OK –Most severe bandwidth limitation in 12-way receiver (ARx12) ~100 MHz Comparative test of digital transmission at 320 Mb/s between existing ARx12 and Zarlink engineering sample Each mounted on test board (clean environment) ARx12 with external fast, self-biased, LVDS-output comparators (ADCMP604) ARx12 Zarlink Comp.

Opto-Rx Measurements for Pixel Upgrade Sender / Receiver Setup Agilent 8110A pulse/pattern generator AOH (TOB type) AOH test setup Tektronix DSA70804 Scope Receiver boards

Opto-Rx Measurements for Pixel Upgrade Test A – Unbalanced Periodal Signals 40 MHz with variable duty cycle (T on /T period ) Considerable distortions up to misinterpretation due to threshold imbalance Bad result. However: This is a very unrealistic situation… Example: 25% duty cycle represents repetitive unbalanced code T on T period CodeSender Opt_Head (analog)ARx12Zarlink %49.8%47.3%50.1% %25.6%32.7%35.3% %12.4%27.0%--- Receiver

Opto-Rx Measurements for Pixel Upgrade Test B – Balanced 320Mb/s with Sequence of 0s or 1s words of programmable pattern filled with PRBS14 (=balanced) Programming 1s (or 0s) from the beginning of the pattern until remaining PRBS bits become corrupted Amazing result: –Zarlink tolerates ~700 consecutive 1s (or 0s) without effect on subsequent pattern –With more than ~700 same symbols, subsequent single bits deteriorate or vanish completely (symmetric behavior) –ARx12 even tolerates ~3000 consecutive 1s Perfectly suitable for pixel system, where even 20 consecutive 1s or 0s are extremely unlikely

Opto-Rx Measurements for Pixel Upgrade Test C – Eye 320Mb/s (1) Optical Head (analog) Limited rise time (mostly due to pattern generator) Stable timing Solid eye opening

Opto-Rx Measurements for Pixel Upgrade Test C – Eye 320Mb/s (2) Zarlink (digital) Perfectly fine High bandwidth (Zarlink can do 1.6Gb/s)

Opto-Rx Measurements for Pixel Upgrade Test C – Eye 320Mb/s (3) ARx12+comparator (digital) Narrow opening with best settings of pulse generator (amplitude), AOH (offset) and Rx12 (offset) Unusable with non- optimal settings (where Zarlink still works perfectly well)

Opto-Rx Measurements for Pixel Upgrade Test Conclusions ARx12 performance is marginal – even on a lab test bench in a noise-free environment Needs careful tuning of parameters in order to work Hence we don’t recommend its use in a production system Zarlink works very well – but is not a commercial product Normally 850nm, this engineering sample has 1310nm photodiode Francois is in contact with manufacturer to see if we can get 200 pcs. of 1310nm wavelength version H. Steininger has proposal to recover the phase for the 320MHz digital data stream at deserializer board on pxFED

Opto-Rx Measurements for Pixel Upgrade Modification of Pixel-FED (1) New daughter board (instead of 3 ADC cards) including Zarlink receiver Don’t need to remove current ARx12  allows easy swapping between old and new systems Need new front panel in any case Keep single slot size Keep VME base board

Opto-Rx Measurements for Pixel Upgrade Modification of Pixel-FED (2) Old ADC card New daughter board Zarlink (mounted on daughter board) Front panel VME board Need higher connectors than now Available from different vendor (samples ordered for compatibility tests) OLD NEW ARx12

CMS Upgrade CERN May 14, 2009 W. Bertl PSI Situation at present 32 cables → layers 1+2 (192 ROCs) 32 cables → layer 3 (128 to 192 ROCs) New Proposed Layout 32 cables → layers 1+4 (320 ROCs) 32 cables → layers 2+3 (256 to 320 ROCs) Required Current / cable IanaIdig AA Max Min average st.dev.[%] (calculated for luminosity = ) Required Current / cable IanaIdig AA Max Min average st.dev.[%] Power for BPix Phase-1 Number of Power cables won’t change!

CMS Upgrade CERN May 14, 2009 W. Bertl PSI Bpix Operation Parameters BPix 2008 | BPix 2013 Luminosity 1 x x x x Power Dissipation1612 W | W Analog Voltage 1.7 V | 1.7 V Digital Voltage 2.5 V | 2.5 V Analog Current 293 A | A Digital Current 446 A | A

CMS Upgrade CERN May 14, 2009 W. Bertl PSI CAEN A4603 Power Supplies Present Limitations Voltage:Set Point (max.)Full Range Output Analog 2.3 V5.7 V Digital 3.0 V6.9 V Current: Analog 6 A~ 6 A Digital 15 A~ 15 A Power (single PSU): each line individuallyboth lines loaded Analog 33 W28 W Digital 99 W88 W 116 W

CMS Upgrade CERN May 14, 2009 W. Bertl PSI Required (max.)*Possible at present (10 34 luminosity) Full Voltage:Analog 7.5 V5.7 V Digital 7.5 V6.9 V Current:Analog 9 A6 A Digital 13 A 14.5 A Power:Analog < 68 W 28 W Digital < 98 W 88 W 166 W !!! 116 W * < 10% contingency included 8 modules in a crate exceed 48V supply capacity by 30% ! Total Power needed: 7.1kW Power loss in cables: 4.5 kW A4603 Requirements