CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng.

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Presentation transcript:

CSE 242A Integrated Circuit Layout Automation Lecture 1: Introduction Winter 2009 Chung-Kuan Cheng

Agenda Introduction to CSE242A class Topics Class assignments and projects Design challenges ITRS Roadmap

Topics of CSE242A ITRS Roadmap and Low Power Design Methodologies Partitioning: (1) Two way partitioning, (2) Multiple way partitioning, (3) Multiple level partitioning, (4) Replication cuts, (5) Performance-driven partitioning, (6) Partitioning for FPGAs. Floorplanning: (1) Floorplanning representations, (2) Block configurations, (3) 3D floorplanning. Placement: (1) Placement algorithms, (2) Local placement, (3) Performance driven placement. Global Routing: (1) Multi-commodity flows, (2) Steiner Trees, (3) Performance driven routing. Detail Routing: (1) Channel routing, (2) Maze routing, (3) PC board routing. Special Net Routing: (1) Bus routing, (2) Clock networks, (3) Net matching, (4) Power/Ground distributions. Cell Layout, Compaction.

Class Assignments Homeworks Projects Divided into phases Report and presentation

Design Challenges Parallel Processing Power Dissipation New Technologies

Theme of Class Combinatorial Algorithms Formulation Engineering Electronic Circuits Physics

Scaling Power Interconnect dominance Current density Copper resistivity increases

New Technologies 3D Extension Heterogeneous System Low K New Tech Optical Carbon Nano Tube (CNT) Atomic Switch Spintronics

Moore’s Law # Trans * 2 / 18 months Product price drop half every 18 month

ITRS Roadmap DRAM ½ pitch (nm) MPU/ASIC m1 ½ pitch High Volumn MPU Chip Size (mm 2 ) 140 Chip local clock (GHz) High Performanc e Vdd Low Power Vdd