Introduction EE1411 Design Rules. EE1412 3D Perspective Polysilicon Aluminum.

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Presentation transcript:

Introduction EE1411 Design Rules

EE1412 3D Perspective Polysilicon Aluminum

EE1413 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

EE1414 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

EE1415 Intra-Layer Design Rules Metal2 4 3

EE1416 Transistor Layout

EE1417 Vias and Contacts

EE1418 Select Layer

EE1419 CMOS Inverter Layout

EE14110 Layout Editor

EE14111 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

EE14112 Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

Introduction EE14113 Packaging

EE14114 Bonding Techniques

EE14115 Package-to-Board Interconnect

EE14116 Package Types