From microelectronics down to nanotechnology

Contents Lithography: scaling x- and y-dimensions MOS transistor physics Scaling oxide thickness (z-dimension) CNT transistors Conducting wires (metals and CNTs) Memories Moore’s law and fabrication economics

Top down nanotechnology Scaling from micrometer down Production-proven techniques Laboratory techniques Laboratory tricks Issues to be tackled: Cost Area Speed Defect density

Writing patterns By pen easy to write anything slow to write long works easy to change your mind in the middle By printing press very fast for large number of copies expensive to make the first copy expensive to make changes

Pen vs. printing press AFM needle electron beam optical projection nanoimprint

Lithography Printing press style: optical: mainstream EUV/X-ray: small linewidth but otherwise problematic imprint: partial solution at the moment; only certain aspects proven Pen-like: electron beam: slow writing speed ion beam: very slow writing speed, ultimate resolution AFM, dip-pen,...

The goal of lithography is to make lines and spaces small (only this will increase device packing density)

Contact/proximity lithography gap light from light source quartz mask with chromium pattern photoresist covered silicon wafer

Resolution= line + space Resolution =3  ( /n)* (gap + ½ thickness ) (Hg-lamp line)436 nm gap between mask and resist g  5 µm dresist thicknessd  1 µm nresist refractive indexn  µm in production 100 nm in research

Projection lithography  Sources of radiation (UV 365 nm-436 nm, DUV 193 nm-248 nm, EUV, X-rays, electrons, ions) Optical system I (lenses, mirrors) Mask (pattern) Optical system II (lenses, mirrors) Numerical aperture NA=sin  Imaging medium (resist) Wafer (with patterns) Wafer stage (alignment mechanism)

Resolution = k 1 /NA Depth of focus = k 2 /NA 2

Resist trimming trick Isotropically etch resist  thinner & narrower lines  line-to-line spacing unchanged Works best for narrow initial lines Used in industry

Phase shift masks (PSM) binary mask (quartz/chrome)phase shift mask (PSM) shifter amplitude intensity resist exposure threshold Conditions for phase shifter:  = 2  L/  = 2  nL/. L(n-1) = /2

Phase Shift Mask Fabrication quartz 2-resist waySingle resist way

PSM produces /2 lines !

X-ray lithography Contact/proximity lithography = 13 nm, resolution very good highly penetrating radiation not sensitive to particles, but need thick metal to block x-rays need 1X original because no x-ray mirrors

Optical vs. X-ray masks -reduction optics-mask is final size -flat structures-highly 3D structures 40 nm of metal stops UV light; Need >1 µm thick metal to stop X-rays

Electron beam lithography (EBL) beam spot size 5 nm easily beam scattering in resist (in all solids) 10 nm can be made, but not easily use higher energy (  heating, charging) use thinner resist (  etch resistance down, defects up)

Spot size vs. linewidth linewidth typically 3*spot size to ensure reproducibility and reduce roughness missing pixels

Raster vs. vector scanning Pixel-by-pixel raster scan; exposure / no exposure decision at each pixel “Intelligent skipping of empty spaces”

EBL pros and cons flexible writing of structures individually writing speed very low indeed  small areas only better resolution  lower writing speed thinner resist better resolution, worse etch and implant resistance, danger of pin hole defects

Nano imprint (NIL) 1X master is pressed against polymer force is used (pressure, temperature, UV) release of the master clearing the bottom residue feature size limited by master fabrication only

NIL results

NIL problems Problem 1: need 1X original pattern (cf. X-ray lithography) Problem 2: need 3D original master Problem 3: Lifetime of the master ? Does repeated contact with the polymer damage or contaminate the master ? Problem 4: Who is the first one to try something really new which may not work in production ?

MOS transistor gate length L g source channel drain field oxide gate polysilicon gate oxide The goal of silicon processing and thin film technology is to control diffusion depths, film thicknesses and interfaces at atomic precision.

MOS gate oxide seem by TEM “Metal” gate made of highly doped polycrystalline silicon Amorphous oxide Single crystalline silicon substrate

Scaling of gate oxide Gate oxide thickness  gate length/50 L g T ox 1960’s30 µm 600 nm 1970’s5 µm200 nm 1980’s1 µm20 nm 1990’s0.35 µm7 nm 2000’s100 nm2 nm

Oxide thickness limitations Leakage current (tunneling) Pinhole defects Trapped charge Interface traps Interface structure (dangling bonds) Crystallization and grain boundaries (not in SiO 2 !)

Leakage current explodes below 2 nm

High-k dielectrics (e.g. HfO 2 ) Because most high dielectric constant materials (high-k) are oxides, some oxygen is present during deposition, and some SiO 2 is formed at the interface. The question is: can you control its formation and thickness with Ångström accuracy ?

EOT: Equivalent Oxide Thickness EOT = (  SiO2 /  high ) * t high-  + t SiO2 where t SiO2 is the interfacial silicon dioxide thickness, if any. ZrO 2 film of 6 nm physical thickness with   23 has EOT  1 nm

Control of oxide layer Gate First High-k/Metal Gate Stacks With Zero SiO x Interface Achieving EOT=0.59 nm for 16 nm Application, VLSI Technology Symposium 2009

Half time

CNT transistors

Transistor characteristics

CNT network transistors (TKK) Random network, many current paths from source to drain. High performance compared with polymer transistors

CNTN transistors (TKK)

CNT circuitry by IBM (2006) The five-stage CMOS type nanotube ring oscillator using palladium p-type gates and aluminum n-type gates. The upper right inset shows the nanotube itself with a diameter of ~2 nm.

CNT transistor time scales 1998 first CNT transistor (FET) 2001 logic gate 2002 Schottky switch 2002 top gate FET 2003 ballistic transport demonstrated 2004 AC characterization 2006 circuit demo, 72 MHz ring oscillator 2015? commercial devices (IBM guess)

Metallization 6 levels of metal, cross section IC complexity increase over time

IC metal wire scaling (by n>1) C’ =  (W/n)L/(T/n) = C R’ =  L/(H/n)(W/n) = n 2 R RC time delay  ’ is then given by  ’ = R’C’ = n 2 RC L H T W metal dielectric While transistor performance improves with downscaling, scaled metal wires are worse !

Electromigration Hu, C.-K. et al: Electromigration of Al(Cu) two-level structures: effect of Cu kinetics of damage formation, J.Appl.Phys. 74 (1993), p. 969 Momentum transfer and displacement of lattice atoms by electrons Depends on bond strength (which can be gauged by melting point) Aluminum, low melting point, 650 o C, low electromigration resistance Copper 1083 o C Tungsten 3387 o C improved EM resistance

Grain size effects in metals Mechanical properties scale beneficially with smaller grain size Thermal properties mostly unchanged Resistivity increases with decreasing grain size Erb et al: in The Nano-Micro Interface, Wiley-VCH 2004

Resistivity depends on patterns! G.B. Alers, J. Sukamto, S. Park, G. Harm and J. Reid, Novellus Systems, San Jose -- Semiconductor International, 5/1/2006 You cannot calculate thickness from resistance R = ρL/Wt because thin film resistivity ρ is linewidth and thickness dependent (use e.g. X-rays to get an independent thickness value)

Grain size affected by: -underlying film (chemistry and texture) -deposition process (sputtering vs. plating; & plating A vs. plating B) -material purity -thermal treatments -geometry of structures on wafer G.B. Alers, J. Sukamto, S. Park, G. Harm and J. Reid, Novellus Systems, San Jose -- Semiconductor International, 5/1/2006

Current density barrier Electromigration limit of metals ca. 1 MA/cm 2

Vertical CNT connections Seeded growth in contact holes

CNT’s show ohmic behaviour at current density 4*10 8 A/cm 2

Flash memory: close to limits tunnel oxide 10 nm interpoly oxide/nitride/oxide 50 nm Gate linewidth 100 nm Limit: thinner tunnel oxide traps charge and does become leaky ( to rewrites)

PCM: phase change memory Chalcogenide materials exhibit 100X resistivity difference between crystalline and amorphous states factor of 2 difference in reflectivity Memory programmed and read electrically and/or optically

GST = Ge 2 Sb 2 Te 5

Chalcogenide PCM Programming pulse: 100 ns GST hot spot heated > 620 o C  molten GST rapid cooling  amorphous GST MΩ resistance Reverse programming: also 100 ns 550 o C, crystallization kΩ resistance

Reliability & problems

Actual GST device

Moore’s law: Intel view YearNodeLgEOT nm30 nm0.8 nm nm20 nm0.7 nm nm15 nm0.6 nm nm10 nm0.5 nm nmnot clear how -carbon nanotubes ? -III-V on Si ? 2019non-electronic devices ? -spintronics -optical devices

Linewidth goes down

Chip size vs. wafer size Chip size determined by: how many functions needed how small lines used Wafer size determined by: production economics

Chip size goes up !

Lithography cost up exponentially

Cost of top-down nanofabrication 28 mask levels with 32 nm minimum lines cost of finished chips 10$/cm 2 cost per mask level = 30 cents/cm 2 lithography equipment cost 35 M$ need to fabricate > cm 2 /year defects: 1 failed devices in 5 million cf. DNA self-assembly: ppm error rates correspond to very slow replication

Continued scaling till Å minimum linewidth 0.04 Å gate oxide thickness 2 mV operating voltage 64 exabit DRAMs (exa = ) This is not a scaled MOS transistor but something completely different But Moore’s law is general; it is about economics of device manufacturing; not about transistors