By: Joaquin Gabriels November 24 th, 2008
Overview of CMOS CMOS Fabrication Process Overview CMOS Fabrication Process Problems with Current CMOS Fabrication Future Changes in CMOS Fabrication
Complementary metal–oxide–semiconductor ( CMOS ) Has many different uses: Integrated Circuits Data converters Integrated transceivers Image sensors Logic circuits en.wikipedia.org/wiki/CMOS
NAND Circuit
lsmwww.epfl.ch/Education/former/ /VLSIDesign/ch02/ch02.html
1. Create a pattern. 2. Oxidize small layer, about 1µm thick. 3. Place photoresist on top of SiO 2 4. Place mask(pattern) above photoresist and expose it to UV light.
1. Etch away SiO 2 using HF acid or plasma. 2. Remove remaining photoresist with acids.
To create a n well: Diffusion Heat wafer in Arsenic gas chamber until diffusion occurs. Ion Implantation Arsenic or phosphorous are implanted in window.
A thin layer of oxide is deposited. A thin layer of polysilicon is deposited using Chemical Vapor Deposition (CVD).
Remove oxide layer using acid. Dope open area using Ion implantation or diffusion.
Optical lithography is limited by the light frequency. Material limitations Yield limitations Space limitations
Material changes like using high-k materials. Design changes SOI(Silicon On Insulator) Double Gate (Finfet) Twin-Tub Process
CMOS Digital Integrated Circuit Design - Analysis and Design by S.M. Kang and Y. Leblebici “Introduction to VLSI Circuits and Systems,” John Wiley and Sons, 2002 /VLSIDesign/ch02/ch02.html users.ece.utexas.edu/~adnan/ vlsi -05/lec0Fab.ppt _ CMOS _Process_Steps/08_Simple_ CMOS _Fab.ppt access.ee.ntu.edu.tw/course/VLSI_design_90second/data/Chapter%203%20Part 2% doc