SEMINAR PRESENTATION ON IC FABRICATION PROCESS PREPARED BY: GUIDED BY: VAIBHAV RAJPUT(12BEC102) Dr. USHA MEHTA SOURABH JAIN(12BEC098)

CONTENTS LATEST TRENDS IN SEMICONDUCTOR MANUFACTURING 3-D IC FABRICATION IC FABRICATION PROCESS BLOG

So far So good! Semiconductor Manufacturing Process um nm um nm um nm um nm um nm nm nm nm nm nm nm nm nm nm nm

DESIGN RULE Some example of DRC's in IC design include: Active to active spacing Well to well spacing Minimum channel length of the transistor Minimum metal width Metal to metal spacing Metal fill density (for processes using CMP) Poly density ESD and I/O rules Antenna effect

DIE SHRINK Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS) Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI) Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture.

Intel CPU core roadmaps

Intel Tick - Tock

Architectural change Fabrication proesss MicroarchitectureCodenamesRelease Date TickDie shrink 65 nm P6, NetBurstPresler, Cedar Mill, YonahJanuary 5, 2006 TockNew michroarchitecture core MeromJuly 27, 2006 TickDie shrink 45 nm PenrynNovember 11, 2007 TockNew michroarchitecture Nehalem November 17, 2008 TickDie shrink 32 nm westmereJanuary 4, 2010 TockNew michroarchitecture Sandy Bridge January 9, 2011 TickDie shrink 22 nm Ivy BridgeApril 29, 2012 TockNew michroarchitecture Haswell June 2, 2013 TickDie shrink 14 nm BroadwellSeptember 8, 2014 TockNew michroarchitecture Skylake 2015 TickDie shrink 10 nm Cannonlake2016 TockNew michroarchitecture 2017 TickDie shrink 7 nm 2018 TockNew michroarchitecture 2019 TickDie shrink 5 nm 2020 TockNew michroarchitecture 2021

FinFET A double-gate FinFET device. An SOI FinFET MOSFET

Tri-gate Transistor Schematic view

3D IC MANUFACTURING TECHNOLOGIES Monolithic Wafer-on-Wafer Die-on-Wafer Die-on-Die

BENIFITS OF 3D ICs Footprint Cost Heterogeneous integration Shorter interconnect Power Design Circuit security

DISADVANTAGES OF 3D IC MANUFACTURING Higher cost Thinning 2 types of die - master and slave Handling/Align Drill holes/fill plug by metal

CHALLENGES FOR 3D IC MANUFACTURING Yield Heat Design complexity Testing Lack of standards Heterogeneous integration supply chain Lack of clearly defined ownership

IC FABRICATION PROCESS

PROCESSING Deposition Removal Patterning Modification of electrical properties physical vapor deposition (PVD) chemical vapor deposition (CVD) electrochemical deposition (ECD) molecular beam epitaxy (MBE) atomic layer deposition (ALD) etch processes (either wet or dry) chemical-mechanical planarization (CMP) lithography diffusion furnaces ion implantation furnace annealing or rapid thermal annealing (RTA)

FRONT-END-OF-LINE PROCESSING FEOL processing refers to the formation of the transistors directly in the silicon

Front-end surface engineering is followed by -  Growth of gate dielectric (SiO 2 )  Patterning of the gate  Patterning of the source and drain regions  Implantation od diffusion of dopants to obtain the desired complementary electrical properties

BACK-END -OF-LINE PROCESSING Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL

WAFER TEST DEVICE TEST DIE PREPARATION PACKAGING

HAZARDOUS MATERIALS Poisonous elemental dopants - arsenic, antimony and phosphorus poisonous compounds - arsine, phosphine and silane Highly reactive liquids - hydrogen peroxide, fuming nitric acid and hydrofluoric acid

REFERENCES 1) Rajendran, Bipin. "Sequential 3D IC Fabrication – Challenges and Prospects." Chomsky Stanford. Department of Electrical Engineering, Stanford University, n.d. Web. 27 Apr ) Patti, Robert. "Impact of Wafer-Level 3D Stacking on the Yield of ICs." Future Fab International. Tezzaron Semiconductor, 07 Sept Web. 27 Apr ) "EDA's Big Three Unready for 3D Chip Packaging." EDA's Big Three Unready for 3D Chip Packaging. EE Times, n.d. Web. 27 Apr ) Dally, William J. "Future Directions for On-Chip Interconnection Networks." OCIN Workshop. 7 Dec Web. 5) Semiconductor device fabrication - 6)3D integrated circuit - 7)Multigate devices -

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