Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS.

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Presentation transcript:

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Manufacturing Process (Courtesy: Prof. Kenneth Laker, U. Penn)

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Process p-p- p+p+ p+p+

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Latch-up problem

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Silicon on insulator(SoI)

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Silicon on insulator(SoI)

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Images after Lithography

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Plasma Etch Tool Dry Etching

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Nitride Etch

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Resist Strip

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Etching

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Etch Wafers in KOH(potassium hydroxide) Wet etching

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Single sided KOH Etch Apparatus

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After KOH Etch

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Deposit Polysilicon

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Deposition

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Polysilicon Deposition

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Hand Spinner Coat(photoresist coating)

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Exposure Tools

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Pattern Developing (hand develop)

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After photolithography

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Polysilicon Etch

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Sputter Aluminium

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Wafer Saw

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Photo cross-section of a transistor

Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Review Questions 1.Described briefly technological steps required to manufacture a CMOS inverter. Clearly specify masks used in each step. Give relevant sketches. 2.Give a brief explanation for the following CMOS process technologies: (i)N-well (ii)P-well (iii)Twin well 3.Why do we need design rules. 4.Contrast the difference between micron rules and scalable rules. Give one advantage for using each design rule type.