COMPET Electronics and Readout Erlend Bolle1,Michael Rissi1, Michelle Böck1, Jo Inge Buskenes1, Kim-Eigard Hines1, Ole Dorholt1, Ole Røhne1, Steinar Stapnes1,2, Jan G. Bjaalie3, Arne Skretting4 1Universitet i Oslo, Norway 2CERN, Geneva, Switzerland 3Department of Anatomy & CMBN, Oslo, Norway 4Rikshospitalet-Radiumhospitalet Medical Center, Oslo, Norway

Detector characteristics Number of channels: 600 LYSO crystals 400 WLS elements Light-yield: LYSO speed: 40 ns LYSO+MPPC: 1300 p.e./511 keV WLS+MPPC: less than 10% MPPC gain: ~1E6 (0.16 pC/p.e.) Event rate: 10 Mcps Expected multiplicity: 20 hits/event

Performance considerations Detector granularity Usability floor: e+ flight and γ-pair accolinearity Energy resolution Determines WLS-coordinate resolution Important for handling Comptons Time resolution Disentangle close-in-time events Maximize useful data throughput Kinematic studies Suppress singles, pileup events Gain stability Monitor rate and spectrum, slow control HV Mechanical precision, stability Not to be taken for granted…

Project constraints Affordability Maintainability Exclude high-speed ADC modules Exclude custom ASIC development Use standard “office grade” components if possible Design, build in-house electronics if necessary Maintainability Modular design Interchangeable parts Automatic calibration Scalability: prototype tests to a few kChannels

System overview TCP/IP Analog preamplifier 1Gbps Switch Computer Farm UDP/IP Analog preamplifier Discriminator LVDS Virtex 5 Readout FPGA 1Gbps Switch Computer Farm data serial link clk Virtex 5 Trigger FPGA Embedded system UDP/IP slow control serial link clk UDP/IP Analog preamplifier Discriminator LVDS Virtex 5 Readout FPGA data HV supply TCP/IP

Coincidence Unit (FPGA) Data Acquisition 011110.. Vthr Analog Electronics Digital Electronics FPGAs Coincidence Unit (FPGA) Analog Electronics Digital Electronics FPGAs 010010..

Front-end electronics Classic Approach Standard shaping Fast channel (trigger) Slow channel (energy) ADC for conversion Time Over Threshold Use Time Over Threshold (TOT) information No ADC needed! Fast digitization using FPGA Timestamping No trigger needed Vthr Vthr Discriminator ADC

Time-over-threshold front-end Folded cascode topology Constant current reset Bias current budget: 15mA/channel All-discrete parts!

Parameterization Filter Readout system: FPGA Fast Digitizer Parameterization Filter Event Builder Ethernet 1Gs sampling rate Continuously sampling No external trigger needed! Extract time and amplitude information TDC/QDC Incremented with each global coincidence All events tagged with global event number 1Gb/s link UDP data packets

Data Flow SSD: up to >500 MBps Magnetic: 80 MBps (more than x10 in price…) Trigger 1Gbps UDP PC PC PC FPGA PC FPGA PC FPGA PC FPGA FPGA Rate: 10 Mcps Event: 4 LYSO hits, 4*4 WLS hits Size: 4 byte/hit -> 1GBps Trigger suppression: 40% -> 400MBps Per PC: 50 MBps (after event building and Zlib compression)

Parameterization Filter FPGA Fast Digitizer Parameterization Filter Event Builder Ethernet 1Gb sampling rate Continuous sampling No external trigger needed! Triggering Extract time and amplitude information TDC/QDC Event number incremented with each global coincidence Events tagged with event number 1Gb/s link UDP data packets

HV supply 400 HV channels 1mV precision Mounted in a 3-unit rack Output to 100V Setting to 1mV precision 400 Channels 3U rack mount Ethernet control 400 HV channels 1mV precision Mounted in a 3-unit rack Picture of cards and rack Imaging 2010, Stockholm

Test Setup 1 LYSO (3×3×100mm3) 5 WLS (1×30×80mm3) 6 MPPC (3×3mm2) Ga-68 source for coincidence measurement Tagger with LYSO(2×2×10mm3) readout by MPPC COMPET readout

Proof of Concept Acquired with the full COMPET readout chain Coincidence part of readout Non-optimal light collection (poor optical contact)

Calibration/linearity Cs-137 Ba-133

Status and outlook System design: Analog front-end: FPGA/Ethernet DAQ Highly scalable Cost effective Analog front-end: Single channels tested 16-channel board assembled, ready for tests FPGA/Ethernet DAQ Single FPGA system tested (self-triggered mode) Trigger- and interface being specified HV system implemented