MIT Lincoln Laboratory NU Status-1 JAB 11/20/2015 Advanced Photodiode Development 7 April, 2000 James A. Burns ll.mit.edu

MIT Lincoln Laboratory NU Status-2 JAB 11/20/2015 3D Photodiode Development Snapshot Goal –Produce high quality photodiodes for visible imaging Standard CMOS processes do not produce image-quality photodiodes Photodiode process must be compatible with 3D integration Approach –Review existing Lincoln silicon-photodiode processes –Optimize an existing process to meet the active pixel sensor requirements using Process and device simulation Additional characterization of existing photodiodes Tasks –Define photodiode requirements –Define photodiode fabrication process –Layout a photodiode test chip –Fabricate and characterize photodiodes 3 runs to optimize device properties 3D integration and photodiode characterization

MIT Lincoln Laboratory NU Status-3 JAB 11/20/2015 Lincoln Silicon Photodiode Survey A comparison of photodiodes and the principal processes which affect dark current

MIT Lincoln Laboratory NU Status-4 JAB 11/20/2015 Photodiode Process 1st Pass Bulk substrate –25-  m epi, 300  -cm –0.01  -cm p-type wafer Process highlights –LOCOS isolation 30-nm stress-relief oxide 20-nm Si 3 N 4 –250-nm field oxide –Dual N + implant Phosphorus to obtain a deep junction Arsenic to maintain high C 0 –Extended anneal to repair N + implant damage Eight Mask Levels –Six through metal-1, passivation –Deep via and back metal for 3D integration tests

MIT Lincoln Laboratory NU Status-5 JAB 11/20/2015 Photodiode Simulations Profile following field oxidation LOCOS bird’s beak limits fill factor Completed simulation indicates a 1-  m junction depth 0.5  m P-type epi XjXj Field Oxide

MIT Lincoln Laboratory NU Status-6 JAB 11/20/2015 Photodiode Test Chip Characterization Front side measurements –Diode leakage vs diode area, perimeter –Cross talk vs diode, isolation spacing –Diode responsivity(  ), dark current, linearity(  ) –Array uniformity and yield Back side measurements –Determine if bond process degrades photodiode –Measure photodiode properties vs silicon thickness 3D imager –Measure photodiode properties vs deep via resistance –Determine whether 3D assembly degrades photodiode –Deep via and back metal layers included in reticle set

MIT Lincoln Laboratory NU Status-7 JAB 11/20/2015 Imager Test Devices Diode Array Array measurements –Leakage and cross talk vs diode area and N + N +, N + P + spacing –Responsivity, linearity, and yield P+ Contacts N+P Diodes Metal-1

MIT Lincoln Laboratory NU Status-8 JAB 11/20/2015 Imager test Devices Edge Effects Diode Measure leakage vs diode area, perimeter to isolate edge effects –LOCOS-induced stress, inadequate channel stop –Misaligned contacts N+P Diodes-5 in parallel N+P Outer Diodes-2 in parallel P+ Contact

MIT Lincoln Laboratory NU Status-9 JAB 11/20/2015 Imager Test Devices Individual Diodes Measure leakage vs isolation features N+-N+ Gap N+P Diode P+ Contact

MIT Lincoln Laboratory NU Status-10 JAB 11/20/2015 Imager test Devices Parasitic FET Characterize leakage mechanisms –separate surface from bulk leakage with metal gate –determine minimum N + separation L g Metal-1 Gate N+P Diode W P+ Contact G o

MIT Lincoln Laboratory NU Status-11 JAB 11/20/2015 Backside Illuminated Characterization Photodiode wafer bonded to support wafer –Silicon thinned –Silicon etched to expose metal-1 pads Standard CCD process for backside imaging Photodiode wafer Support wafer + Silicon Oxide Metal-1 Bond layerN + Silicon Support wafer Completed backside imager  Support wafer

MIT Lincoln Laboratory NU Status-12 JAB 11/20/2015 3D Assembly Characterization Photodiode wafer bonded to oxidized silicon wafer –Silicon removed from transfer wafer –Deep vias etched and connections made to metal-1 of photodiode wafer Assembly bonded to support wafer –Silicon thinned –Silicon etched to expose metal-1 pads Photodiode wafer Transfer wafer + Photodiode wafer  Completed backside imager Support wafer

MIT Lincoln Laboratory NU Status-13 JAB 11/20/2015 Photodiode Development Status Silicon photodiode process survey complete Initial process defined; optimization via simulation underway Test devices defined; layout nearly complete