The threshold voltage for long channel transistors V T0 is defined as: Eindhoven MOS-AK Meeting April 4, 2008 Eindhoven MOS-AK Meeting April 4, 2008 Accurate FinFET modeling at high temperatures A.Cerdeira 1, M. Estrada 1, J. Alvarado 2, V. Kilchytska 2 and D. Flandre 2 1 Sección de Electrónica del Estado Sólido, Depto. de Ingeniería Eléctrica CINVESTAV, México, D.F. 2 Microelectronics Laboratory, Université Catholique de Louvain, Louvain-la-Neuve, Belgium INTRODUCTION The new compact analytical Doped Symmetric Double-Gate Model (Doped-SDG model) recently developed in [1,2,3] that considers variable mobility and short-channel effects, is used for modeling FinFETs behavior at different temperatures up to 200°C. FinFETs with the following features are analyzed [4]:  High K-metal gate stack.  Na= cm -3.  EOT = 1.6 nm.  Fin-width of 25 nm.  Fin-height of 65 nm.  5 Fins.  Transistor channel width, W=775 nm.  Channel lengths of 10  m and 80 nm. SEM photo of a FinFET structure from IMEC Comparison of measured and modeled transfer characteristics at V D = 20 mV and 1V with temperatures of 20°C; 75°C; 100°C; 150°C and 200°C are shown in figures 1 to 4. Excellent agreement in below and above threshold regions is observed including the variation of the subthreshold slope. Extracted values of the model parameters are also show in Tables I - III with = 0.6 for all cases. Gate Drain Source Multiple Fins Fin-height Fin-width Channel length DOPED-SDG MOSFET MODEL As was shown in [1] the new model is based on the description of the potential difference between the surface and the center of the silicon layer,  d, as function of doping concentration Na, equivalent gate dielectric thickness t ox and silicon layer thickness t s. The surface potentials in all regimes, from below to above threshold regime can be calculated using the Lambert function. The inverted charge concentration normalized to gate capacitance C ox and multiplied by thermal voltage  t =kT/q is equal to [2,3]: The mobility dependence at transversal medium electric field Em, at electric field along the channel and at temperature T is expressed as: ; where q ns and q nd are normalized inverted charge concentrations at source and drain respectively. Current including the short channel effects (SCE) and temperature is equal: V GT = V G - V T and SCE are considered through the following expressions:  VT including DIBL and roll-off effect (V T = V T0 -  V T ) Variation of S Saturation voltage Channel shorteningEffective drain voltage V Def Natural DG length  o (cm 2 /V s) E1 (V/cm) P1 E2 (V/cm) P2 L= 10  m  V Def 1.5 L= 80 nm – 2  V Def 1.5 T ºC R [  ]  S (mV/dec)T=20ºC L= 10  m (exp) modeled L= 80 nm (exp) modeled Fig. 1 Transfer characteristic at 20 mV; L= 10  m Fig. 2 Transfer characteristic at 1 V; L= 10  m Fig.3 Transfer characteristic at 20 mV; L= 80 nm Fig. 4 Transfer characteristic at 1 V; L= 80 nm TABLE I Mobility parameters  o, E1, P1, E2, P2 TABLE II Series resistance and parameter  TABLE III Extracted values of subthreshold slope S CONCLUSIONS The Doped-SDG Model was used for modeling FinFET transistors with metal gate, low doped silicon layer for two different channel lengths, 10  m and 80 nm. The transfer characteristics were measured at 20ºC, 75ºC, 100ºC, 150ºC and 200ºC. The measured and modeled characteristics present an excellent coincidence from below to above threshold regions, including the subthreshold slope, showing the accuracy of the proposed model and its application to FinFETs. BIBLIOGRAPHY [1] A. Cerdeira, O. Moldovan, B. Iñiguez and M. Estrada, “Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETs”, Solid-State Electronics, Jan. 2008, available on ine [2] A. Cerdeira, B. Iñiguez and M. Estrada, “Improved Compact Model for Symmetric Doped Double-Gate MOSFETs”, SBMicro 2007, ECS Transactions, 9 (1) (2007) [3] A. Cerdeira, B. Iñiguez and M. Estrada, “Compact Model for Short Channel Symmetric Doped Double-Gate MOSFETs”, to be published in Solid-State Electronics [4] N. Collaert et al.,Symposium on VLSI Technology, pp , 2005