Verification Methodology of Gigabit Switch System 1999/9/9 Yi Ju Hwan.

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Presentation transcript:

Verification Methodology of Gigabit Switch System 1999/9/9 Yi Ju Hwan

Agenda o Design flow & Verification o Example u Algorithm-level design & verification u RT-level design & verification u Gate-level verification o Introduction to Gigabit project o Verification methodology of gigabit switch system o Summary

Design Flow Create ProjectSpec. Decision Spec.

Design Flow Spec. Design Design & Coding Simulation Verification Tape-out

Design Flow Fabrication CHIP!!! Testing

Design & Verification Example Motion picture MPEG encoding MPEG bit stream Broadcast system

Algorithm-level Design & Verification MPEG encoding Algorithm level Model Motion picture file MPEG file MPEG player

RT-level Design & Verification Motion picture file MPEG file MPEG player Broadcast system interface model MPEG encoder model Camera interface Model

Gate-level Verification (Hardware Emulation) Motion picture MPEG bit stream Broadcast system Emulator

Gigabit Ethernet Switch Project o 8x8 Switch Fabric u 16 Gbps bandwidth o Gigabit Port Controller u Individual lookup engine u Full gigabit line-rate support SF PC NP GMII

Expansion o 32x32 Switch with 12 SF, 32 PC SF PC SF PC SF NP SF PC NP SF PC SF PC SF NP SF PC NP

Verification Strategy o Architecture-level verification u High-level description in C-language u Decision making about expansion scheme, architecture o Simulation with network environment model u RT-level description in Verilog HDL u Actual design & debugging with Virtual Network o Software emulation u PC with Verilog simulator u Verification with real network environment o Hardware emulation u Hardware prototype board with FPGA u Verification with other chipset (network processor, MAC interface)

Building Environment Model (Virtual Network) o Captured packets u Real application program u Controlled traffic Use traffic generation routine of network simulator u Various packets TCP, UDP, ARP, IPX... RealNetworkEnvironment Packetcapture Analysis & Filtering VirtualNetworkEnvironment

GESIM(Architecture-level Verification) VnetVnetI/FTx VnetI/FRx Model PC PC SF Simulator EventHandlerScheduler Receivedpackets ExecutorEventQueue Parameters Packets to be sent DebuggerUnit

C routine Virtual Network with PLI(RT- level Design & Verification) VnetVnetI/FTx VnetI/FRx Verilog Simulator PC PC SF Receivedpackets Parameters Packets to be sent MACinterface(PLI) MACinterface(PLI)

Software Emulation RealNetworkEnvironment MAC(NIC) MAC(NIC) PC PC SFMACinterface(PLI) MACinterface(PLI) NetworkProcessor(PLI) SSRAMSDRAM SSRAMSDRAM PCVerilogSimulator

Advantage & Disadvantage of Software Emulation o No design change o Easy to debug o Easy to build system u No hardware design overhead o Functionality check with real network system o No hardware interface verification o Slow emulation speed u 300k gate RTL simulation: MHz Ultra Sparc with VCS

Hardware Emulation RealNetworkEnvironment PHYPC(FPGA)SF(FPGA) NetworkProcessor SSRAMSDRAM MAC(LUC3M08) PHYPC(FPGA) SSRAMSDRAM MAC(LUC3M08) Prototype board

Summary o Spec. decision u Architecture level-simulation & verification o Design u System modeling u RT-level simulation & verification o Emulation u Prototype board, Emulator, FPGA