Randal E. Bryant Carnegie Mellon University CS:APP CS:APP Chapter 4 Computer Architecture SequentialImplementation CS:APP Chapter 4 Computer Architecture SequentialImplementation

– 2 – CS:APP Y86 Instruction Set Byte pushl rA A0 rA F jXX Dest 7 fn Dest popl rA B0 rA F call Dest 80 Dest rrmovl rA, rB 20 rArB irmovl V, rB 30F rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 00 halt 10 addl 60 subl 61 andl 62 xorl 63 jmp 70 jle 71 jl 72 je 73 jne 74 jge 75 jg 76

– 3 – CS:APP Computing with Logic Gates Outputs are Boolean functions of inputs

– 4 – CS:APP Bit Equality Bit equal a b eq bool eq = (a&&b)||(!a&&!b)

– 5 – CS:APP Word Equality 32-bit word size b 31 Bit equal a 31 eq 31 b 30 Bit equal a 30 eq 30 b1b1 Bit equal a1a1 eq 1 b0b0 Bit equal a0a0 eq 0 Eq = = B A Word-Level Representation bool Eq = (A == B)

– 6 – CS:APP OF ZF CF OF ZF CF OF ZF CF OF ZF CF Arithmetic Logic Unit Combinational logic Continuously responding to inputs Control signal selects function computed Corresponding to 4 arithmetic/logical operations in Y86 Also computes values for condition codes ALUALU Y X X + Y 0 ALUALU Y X X - Y 1 ALUALU Y X X & Y 2 ALUALU Y X X ^ Y 3 A B A B A B A B

– 7 – CS:APP Bit-Level Multiplexor Control signal s Data signals a and b Output a when s = 1, b when s = 0 Bit MUX b s a out bool out = (s&&a)||(!s&&b)

– 8 – CS:APP Word Multiplexor Select input word A or B depending on control signal s Word-Level Representation b 31 s a 31 out 31 b 30 a 30 out 30 b0b0 a0a0 out 0 int Out = [ S = 1 : A; S = 0 : B; ]; s B A Out MUX

– 9 – CS:APP Random-Access Memory Stores multiple words of memory Address input specifies which word to read or write Register file Holds values of program registers %eax, %esp, etc. Register identifier serves as address »ID 8 implies no read or write performed Multiple Ports Can read and/or write multiple words in one cycle »Each has separate address and data input/output Register file Register file A B W dstW srcA valA srcB valB valW Read portsWrite port Clock

– 10 – CS:APP Building Blocks Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control Storage Elements Store bits Addressable memories Non-addressable registers Register file Register file A B W dstW srcA valA srcB valB valW Clock ALUALU fun A B MUX 0 1 =

– 11 – CS:APP SEQ Hardware Structure State Program counter register (PC) Condition code register (CC) Register File Memories Access same memory space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter Instruction memory Instruction memory PC increment PC increment CC ALU Data memory Data memory Fetch Decode Execute Memory Write back icode, ifun rA,rB valC Register file Register file AB M E Register file Register file AB M E PC valP srcA,srcB dstA,dstB valA,valB aluA,aluB Bch valE Addr, Data valM PC valE,valM newPC

– 12 – CS:APP SEQ Stages Fetch Read instruction from instruction memoryDecode Read program registersExecute Compute value or addressMemory Read or write data Write Back Write program registersPC Update program counter Instruction memory Instruction memory PC increment PC increment CC ALU Data memory Data memory Fetch Decode Execute Memory Write back icode, ifun rA,rB valC Register file Register file AB M E Register file Register file AB M E PC valP srcA,srcB dstA,dstB valA,valB aluA,aluB Bch valE Addr, Data valM PC valE,valM newPC

– 13 – CS:APP Instruction Decoding Instruction Format Instruction byteicode:ifun Optional register byterA:rB Optional constant wordvalC 50 rArB D icode ifun rA rB valC Optional

– 14 – CS:APP Executing Arith./Logical Operation Fetch Read 2 bytesDecode Read operand registersExecute Perform operation Set condition codesMemory Do nothing Write back Update register PC Update Increment PC by 2 OPl rA, rB 6 fn rArB

– 15 – CS:APP Stage Computation: Arith/Log. Ops Formulate instruction execution as sequence of simple steps Use same general form for all instructions OPl rA, rB icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory R[rB]  valE Write back Write back result PC  valP PC update Update PC

– 16 – CS:APP Executing rmmovl Fetch Read 6 bytesDecode Read operand registersExecute Compute effective addressMemory Write to memory Write back Do nothing PC Update Increment PC by 6 rmmovl rA, D ( rB) 40 rA rB D

– 17 – CS:APP Stage Computation: rmmovl Use ALU for address computation rmmovl rA, D(rB) icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valC  M 4 [PC+2] valP  PC+6 Fetch Read instruction byte Read register byte Read displacement D Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB + valC Execute Compute effective address M 4 [valE]  valA Memory Write value to memory Write back PC  valP PC update Update PC

– 18 – CS:APP Executing popl Fetch Read 2 bytesDecode Read stack pointerExecute Increment stack pointer by 4Memory Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 popl rA b0 rA F

– 19 – CS:APP Stage Computation: popl Use ALU to increment stack pointer Must update two registers Popped value New stack pointer popl rA icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[ %esp ] valB  R [ %esp ] Decode Read stack pointer valE  valB + 4 Execute Increment stack pointer valM  M 4 [valA] Memory Read from stack R[ %esp ]  valE R[rA]  valM Write back Update stack pointer Write back result PC  valP PC update Update PC

– 20 – CS:APP Executing Jumps Fetch Read 5 bytes Increment PC by 5Decode Do nothingExecute Determine whether to take branch based on jump condition and condition codesMemory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch jXX Dest 7 fn Dest XX fall thru: XX target: Not taken Taken

– 21 – CS:APP Stage Computation: Jumps Compute both addresses Choose based on setting of condition codes and branch condition jXX Dest icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Fall through address Decode Cnd  Cond(CC,ifun) Execute Take branch? Memory Write back PC  Cnd ? valC : valP PC update Update PC

– 22 – CS:APP Executing call Fetch Read 5 bytes Increment PC by 5Decode Read stack pointerExecute Decrement stack pointer by 4Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest call Dest 80 Dest XX return: XX target:

– 23 – CS:APP Stage Computation: call Use ALU to decrement stack pointer Store incremented PC call Dest icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Compute return point valB  R[ %esp ] Decode Read stack pointer valE  valB + –4 Execute Decrement stack pointer M 4 [valE]  valP Memory Write return value on stack R[ %esp ]  valE Write back Update stack pointer PC  valC PC update Set PC to destination

– 24 – CS:APP Executing ret Fetch Read 1 byteDecode Read stack pointerExecute Increment stack pointer by 4Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address ret 90XX return:

– 25 – CS:APP Stage Computation: ret Use ALU to increment stack pointer Read return address from memory ret icode:ifun  M 1 [PC] Fetch Read instruction byte valA  R[ %esp ] valB  R[ %esp ] Decode Read operand stack pointer valE  valB + 4 Execute Increment stack pointer valM  M 4 [valA] Memory Read return address R[ %esp ]  valE Write back Update stack pointer PC  valM PC update Set PC to return address

– 26 – CS:APP Computation Steps All instructions follow same general pattern Differ in what gets computed on each step OPl rA, rB icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte [Read constant word] Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory [Memory read/write] R[rB]  valE Write back Write back ALU result [Write back memory result] PC  valP PC update Update PC icode,ifun rA,rB valC valP valA, srcA valB, srcB valE Cond code valM dstE dstM PC

– 27 – CS:APP Computation Steps All instructions follow same general pattern Differ in what gets computed on each step call Dest Fetch Decode Execute Memory Write back PC update icode,ifun rA,rB valC valP valA, srcA valB, srcB valE Cond code valM dstE dstM PC icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 valB  R[ %esp ] valE  valB + –4 M 4 [valE]  valP R[ %esp ]  valE PC  valC Read instruction byte [Read register byte] Read constant word Compute next PC [Read operand A] Read operand B Perform ALU operation [Set condition code reg.] [Memory read/write] [Write back ALU result] Write back memory result Update PC

– 28 – CS:APP Computed Values Fetch icodeInstruction code ifunInstruction function rAInstr. Register A rBInstr. Register B valCInstruction constant valPIncremented PCDecode srcARegister ID A srcBRegister ID B dstEDestination Register E dstMDestination Register M valARegister value A valBRegister value BExecute valEALU result CndCondition flagMemory valMValue from memory

– 29 – CS:APP SEQ Summary Implementation Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logicLimitations Too slow to be practical In one cycle, must propagate through instruction memory, register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle