Computer Systems Organization and Architecture

 This course covers the following topics: Introduction to computer evolution, technology trends, system performance by Amdhal’s law. Computer structure that consists of structure & function of computer system, bus systems and bus arbitrations. Instruction Set Architecture (ISA) such as instruction set design issue and classifying ISA. Memory addressing such as addressing mode, CISC and RISC. ALU design. Computer architecture using MIPS architecture. Computer memory such as main memory design, memory hierarchy design, cache performance and virtual memory for paging and segmentation. Pipelining such as instruction pipeline, MIPS pipeline, pipelined vector processor and RISC pipelining. Parallel processors such as SIMD, MIMD, processors array, superscalar and I/O devices such as hard disk, RAID and multicore programming.

 Minimum 80% – MONDAY TUESDAY Consultation KT6144 / KT6213 WEDNESDAY THURSDAY KT6144 / KT6213 DK4 FKAB FRIDAY

ItemsWeightage Quizzes / Test20% - 30% Assignments / Project10% - 30% Final Exam30% - 50% TOTAL100% We shall assign you : Items Assignments Project Mid-Semester Test Final Exam

Hennessy, J.L. & Patterson, P.A Computer architecture: A quantitative approach, 4 th Ed., Elsevier Science and Technology Book. Hesham El-Rewini, Mostafa Abd-El-Barr Advanced computer architecture and parallel processing, Wiley. Hill, M.D Fault tolerant computer architecture, Morgan & Claypool Publishers. Keckler, S.W., Olukotun K., Hofstee. H.P Multicore processors and systems, Springer. Author: William Stallings Title: Computer Organization and Architecture Edition: 2010, 8 th Edition Publisher: Pearson

WeekDateTopicsLecturer Sep Introduction Dr. Nasharuddin Zainal Sep Computer Structure Sep Instruction Set Architecture (ISA) 43-7 Oct Instruction Set Architecture (ISA) Oct Data Representation Oct Parallel Processor Oct Addressing Modes 831 Oct – 4 Nov Mid Semester Exam Nov Computer Architecture Prof. Dr. Kasmiran Jumari Nov Pipelining 1128 Nov – 2 Dec Computer Memory Dec Virtual Memory Dec I/O Devices Dec Operating Systems and applications Sem break: 7-11 Nov 2011 Exam starts : 3-20 Jan 2012

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 Ability to apply transfer register notation to describle data flow in CPUs  Ability to explain interrupt operation and exception handling mechanisms  Ability to compare main and virtual memory, and cache systems operation  Ability to design datapath logic in CPUs and microprogrammed control units