Chap. 8 Sequencing and Control A Simple Computer Architecture A Simple Computer Architecture Single-Cycle Hardwired Control Single-Cycle Hardwired Control.

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Presentation transcript:

Chap. 8 Sequencing and Control A Simple Computer Architecture A Simple Computer Architecture Single-Cycle Hardwired Control Single-Cycle Hardwired Control Multiple-Cycle Multiprogrammed Control Multiple-Cycle Multiprogrammed Control

Instructions Instruction Instruction –A collection of bits that instructs the computer to perform a specific operation »Opcode: operation code If the opcode consists of m bits, … If the opcode consists of m bits, … »Instruction set Program Program –A list of instructions

Instruction formats R1  R2 – R3 R2  R7 + 3 Examples) If R6 = 0, PC  PC-20 Address offset

Sequencing Two address in a microinstruction Two address in a microinstruction – 분기가능한 두 가지 address 를 준비 CAR: Counter with parallel load CAR: Counter with parallel load – 분기할 주소 계산 –Program Counter (PC)

Instruction formats If R6!=0, Then, …

Instruction Instruction Opcode Micro-operation Decoder

Storage Resources

Single-cycle Hardwired Control Single-cycle computer ; obtain and execute an instruction from the instruction memory all in a single clock cycle

Instruction Decoder Cf) In micro-programmed control, Control memory PL=1 : jump or branch PL=0 : PC++ PL=1, JB=1 : unconditional jump PL=1, JB=0 : conditional branch Condition for branch (BC) 000 : C 001 : N 010 : V 011 : Z 100 : /C 101 : /N 110 : /V 111 : /Z

Instruction Decoder Boolean eq. for decoding ?

Sample Instruction & Program 16bit 로 확장

Limitations of Single-cycle Computer Require multiple clock cycles for performing complex operations Require multiple clock cycles for performing complex operations –Multiplication: add-and-shift Two read accesses of memory for executing an instruction Two read accesses of memory for executing an instruction –Two types of memory: for instruction and data –Load a data word from memory into a register »Two clock cycles are required. Lower limit on the clock period based on a long worst case delay path Lower limit on the clock period based on a long worst case delay path –Pipelining control

Limitations of Single-cycle Computer A solution to the above limitations A solution to the above limitations –Multiple-cycle Micro-programmed Control

Multiple-Cycle Microprogrammed Control

Multiple-Cycle Micro-programmed Control

Microprogram Design

Hardwired Alternative

Pipeline Control