L05 – Logic Synthesis Fall /19/02 Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs I 00 I 01 I 10 I 11 A B A B A B A B Y DecoderSelector Multiplexers can be partitioned into two sections. A DECODER that identifies the desired input,and a SELECTOR that enables that input onto the output. A decoder generates all possible product terms for a set of inputs

L05 – Logic Synthesis Fall /19/02 Shared Decoding Logic A B C in S C out There’s an extra level of inversion that isn’t necessary in the logic. However, it reduces the capacitive load on the module driving this one. These are just “DeMorgan”ized NOR gates Made from PREWIRED connections, and CONFIGURABLE connections that can be either connected or not connected We can build a general purpose “table-lookup” device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device Decoder Configurable Selector This ROM stores 16 bits in 8 words of 2 bits. Fixed “AND plane” Configurable “OR plane”

L05 – Logic Synthesis Fall /19/02 ROM-Based Design Once we’ve written out the truth table we’ve basically finished the design Possible optimizations: - Addressing tricks Truth Table for a 7-sided Die - Eliminate redundant outputs T VX U YZ W

L05 – Logic Synthesis Fall /19/02 Standard Cells First, a library of fixed-pitch logic cells (gates, registers, muxes, adders, I/O pads, …) are created. A data sheet for each cell describes its function, area, power, propagation delay, output rise/fall time as function of load, etc. AOI.21 ABCABC Z DQ DREG

L07 – FSMs – Fall /26/02 Now put it in Hardware! ROM 16x4 unlock Next stateCurrent state IN Trigger update periodically (“clock”) 33 4 inputs  2 4 locations each location supplies 4 bits We assume inputs are synchronized with clock…