PRESENTED BY YONGQUAN CHAI VIKRAM MADINENI

 INTRODUCTION TO VENDING MACHINES  VENDING MACHINE CONTROLLER  DESIGN AND PROGRAMMING  CONCLUSION & FUTURE SCOPE

 The history of Vending Machine (or” automatic retailing “as it is increasingly known) dates back to the time of B.C.  In the early 1880’s first commercial coin operated vending machines were installed in London to dispense the stamps.  The first vending machines in USA were installed in the year 1888 by the Thomas Adams Gum Company and it sold Tutti- Fruiti gum.  Now Vending Machines offer everything stamps, food products, drinks,cigars etc. and have become a part of our lives.

 Most of the vending machines being used are microcontroller based and as the number of functions and products increase, the complexity of controller is also increased.  We feel VHDL program is less complex and cost effective when implemented small scale vending machine.  We have developed VHDL code for a vending machine, which will be targeting small Offices, Motels etc. where the number of products required is limited.

Block Diagram Vending Machine Money Return all Money Selection Clock Deliver Door Money Return  Money can be inserted in the combination of nickel, dime, quarter or dollar.  Three products are available – 1. Pepsi 2. Cookies 3. Chips  Selection is done at the input FIGURE 1

Release PepsiRelease CookiesRelease Chips No Yes >50c =65c=65c =60c=60c =50c=50c <60c Release Changes Change Available ? Return All Money Cookies ChipsPepsi START Select the Prodc ut Insert Money – Nickel, Dime, Quarter or Dollar >65c Chec k Sum Chec k Sum Chec k Sum < 50c >60c <65c FLOW CHART

State Assignment S0: Waiting for money or other instruction S1:Custom selection (10: Cookies, 01: Pepsi, 11: Chips) S2:Total money condition 1 (buying Pepsi) S3:Total money condition 2 (buying Cookies) S4: Total money condition 3 (buying Chips) S5:Deliver Pepsi S6:Availability of changes S7:Return Change S8:Return all money S9:Deliver Cookies S10:Deliver Chips

Mny’, Rtn Sum =60 Sum >65 Sum =65 Sum<65 Sum=50 Change Available Sum>50 Sum<50 Sel:10 Sum<60 Sel:01 Sel:11 Sum>60 S0 S1 S2 S3 S4 S5S6 S7 S8 S9S1 0 Mny, Rtn’ Mny’, Rtn’ Sel:11 Sel:01 Sel:10 FIGURE 2 STATE DIAGRAM OF VENDING MACHINE CONTROLLER

Pepsi Pepsi Cookies CookiesChips Return All Money Return Changes S0 S0 if Myn=0&Rtn=0 S1 if Mny=1&Rtn=0 S8 if Mny=0&Rtn= S1 S2 if Sel01=1 S3 if Sel10=1 S4 if Sel11= S2 S0 if Sum<50c S5 if Sum=50c S6 if Sum>50c S3 S0 if Sum<60c S9 if Sum=60c S6 if Sum>60c S4 S0 if Sum<65c S10 if Sum=65c S6 if Sum>65c S5S0____10000 S6 S7 if CA=1 S8 if CA=0 __00000 S7 S5 if Sel01=1 S9 if Sel10=1 S10 if Sel11= S8S0____00010 S9S0____01000 S10S0____00100 State Table Outputs Next State Present State TABLE 1

BEHAVIOR ARCHITECTURE PROGRAM entity Vend is port ( Mny : in bit_vector (3 downto 1); Sel : inout bit_vector (2 downto 1); Rt,Clk,Ca : in bit; Pe,Co,Ch,Rm,Rc : out bit ); end vend; architecture Vend_bhv of vend is signal S,NS : integer :=0; signal Sum : integer:=0; function Sum1 (Mny : in bit_vector(3 downto 1)) return integer is variable Sum2 : integer :=0; begin case Mny is entity Vend is port ( Mny : in bit_vector (3 downto 1); Sel : inout bit_vector (2 downto 1); Rt,Clk,Ca : in bit; Pe,Co,Ch,Rm,Rc : out bit ); end vend; architecture Vend_bhv of vend is signal S,NS : integer :=0; signal Sum : integer:=0; function Sum1 (Mny : in bit_vector(3 downto 1)) return integer is variable Sum2 : integer :=0; begin case Mny is when "001" => Sum2:= Sum2+1; when "010" => Sum2:=Sum2+2; when "011" => Sum2:=Sum2+5; when "100" => Sum2:= Sum2+20; when others => null; end case; return Sum2; end Sum1; begin process ( clk,S) begin Case S is when 0 => Pe if Sel ="01" then NS Sum 10 then NS Pe if Sel ="01" then NS Sum 10 then NS <=6; end if;

when 3 => Sum 12 then NS Sum 13 then NS Rc if Ca='0' then NS Rc Sum 12 then NS Sum 13 then NS Rc if Ca='0' then NS Rc <='1'; if Sel ="01" then NS <=5; end if; if Sel ="10" then NS <=9; end if; if Sel ="11" then NS <=10; end if; when 8 => Rm Rc Rc null; end case; end process; process (clk) begin if clk='1' then S Rm Rc Rc null; end case; end process; process (clk) begin if clk='1' then S <= NS; end if; end process; end vend_bhv;

PLOT 1 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF CHIPS

PLOT 2 BEHAVIOR ARCHITECTURE WAVEFORM FOR RELEASE OF COOKIES

DESIGN PROCEDURE FOR STRUCTURAL ARCHITECTURE Return All Money Sum Signals Generation Block Vending Machine Controller Nickel Dime Quarter Dollar Pepsi Cookies Chips Money Availability of Changes Clock Release Pepsi Release Cookies Release Chips Return all Money Return Changes FIGURE 3

Return all Money Sum>65c Sum>60c Sum=60c Sum<60c Sum>50c Sum=50c Sum<50c Chips Money Pepsi Availability of Changes Cookies Sum<65c Sum=65c Clock Release Pepsi Release Cookies Vending Machine Controller Release Chips Return All Money Return Changes FIGURE 4

TABLE 2 EXPANDED STATE TABLE FOR DESIGINING THE STRUCTURAL ARCHITECTURE

entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit); end vm; S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit); end vm; architecture vm_structural of vm is signal S:bit_vector(24 downto 0); signal Q:bit_vector(3 downto 0):="0000"; signal D:bit_vector(3 downto 0); signal N:bit_vector(14 downto 0); signal T:bit_vector(5 downto 0); signal QN:bit_vector(3 downto 0):="1111"; component xor2 port(a,b:in bit;c:out bit); end component; component and4 port(a,b,c,d:in bit;e:out bit); end component; component and5 port(a,b,c,d,e:in bit;f:out bit); end component; component and6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component and7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component or5 port(a,b,c,d,e:in bit;f:out bit); end component; component or6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component or7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component not2 port(a:in bit;c:out bit); end component; component DFF port(D,clk:in bit;Q:inout bit;QN:inout bit:='1'); end component; begin not21:not2 port map(Mny,N(0)); not22:not2 port map(Rtn,N(1)); not23:not2 port map(Sel01,N(2)); not24:not2 port map(Sel10,N(3)); not25:not2 port map(sel11,N(4)); not26:not2 port map(S50l,N(5)); not27:not2 port map(S50e,N(6)); not28: not2 port map(S50m,N(7)); not29:not2 port map(S60l,N(8)); not210:not2 port map(S60e,N(9)); not211:not2 port map(S60m,N(10)); not212:not2 port map(S65l,N(11)); architecture vm_structural of vm is signal S:bit_vector(24 downto 0); signal Q:bit_vector(3 downto 0):="0000"; signal D:bit_vector(3 downto 0); signal N:bit_vector(14 downto 0); signal T:bit_vector(5 downto 0); signal QN:bit_vector(3 downto 0):="1111"; component xor2 port(a,b:in bit;c:out bit); end component; component and4 port(a,b,c,d:in bit;e:out bit); end component; component and5 port(a,b,c,d,e:in bit;f:out bit); end component; component and6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component and7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component or5 port(a,b,c,d,e:in bit;f:out bit); end component; component or6 port(a,b,c,d,e,f:in bit;g:out bit); end component; component or7 port(a,b,c,d,e,f,g:in bit;h:out bit); end component; component not2 port(a:in bit;c:out bit); end component; component DFF port(D,clk:in bit;Q:inout bit;QN:inout bit:='1'); end component; begin not21:not2 port map(Mny,N(0)); not22:not2 port map(Rtn,N(1)); not23:not2 port map(Sel01,N(2)); not24:not2 port map(Sel10,N(3)); not25:not2 port map(sel11,N(4)); not26:not2 port map(S50l,N(5)); not27:not2 port map(S50e,N(6)); not28: not2 port map(S50m,N(7)); not29:not2 port map(S60l,N(8)); not210:not2 port map(S60e,N(9)); not211:not2 port map(S60m,N(10)); not212:not2 port map(S65l,N(11)); STRUCTURALPROGRAM FOR MAIN BLOCK

not213:not2 port map(S65e,N(12)); not214:not2 port map(S65m,N(13)); not215:not2 port map(CA,N(14)); and61:and6 port map(QN(3),QN(2),QN(1),QN(0),N(0),Rtn,S(0)); and71:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(1)); and72:and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),S65e,N(13),S(2)); and51:and5 port map(QN(3),Q(2),Q(1),QN(0),N(14),S(3)); xor21:xor2 port map(Sel10,N(4),T(0)); and62:and6 port map(QN(3),Q(2),Q(1),Q(0),N(2),T(0),S(4)); or51:or5 port map(S(0),S(1),S(2),S(3),S(4),D(3)); DFF1:DFF port map(D(3),Clk,Q(3),QN(3)); and52:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel11,S(5)); and73:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(6)); and74:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(7)); and75:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(8)); and76:and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),N(12),S65m,S(9)); and53:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(10)); and77:and7 port map(QN(3),Q(2),Q(1),Q(0),Sel01,N(3),N(4),S(11)); or71:or7 port map(S(5),S(6),S(7),S(8),S(9),S(10),S(11),D(2)); DFF2:DFF port map(D(2),Clk,Q(2),QN(2)); and54:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel01,S(12)); and55:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(13)); and78:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(14)); and79:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(15)); xor22:xor2 port map(S65e,S65m,T(1)); and64:and6 port map(QN(3),Q(2),QN(1),Q(0),N(11),T(1),S(16)); and56:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(17)); and710:and7 port map(QN(3),Q(2),Q(1),Q(0),N(2),N(3),Sel11,S(18)); or72:or7 port map(S(12),S(13),S(14),S(15),S(16),S(17),S(18),D(1)); DFF3:DFF port map(D(1),Clk,Q(1),QN(1)); and65:and6 port map(QN(3),QN(2),QN(1),QN(0),Mny,N(1),S(19)); and57:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(20)); and711:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(21)); and712:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(22)); and58:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(23)); xor23:xor2 port map(Sel01,Sel10,T(2)); and66:and6 port map(QN(3),Q(2),Q(1),Q(0),N(4),T(2),S(24)); or61:or6 port map(S(19),S(20),S(21),S(22),S(23),S(24),D(0)); DFF4:DFF port map(D(0),Clk,Q(0),QN(0)); and41:and4 port map(QN(3),Q(2),QN(1),Q(0),Rpp); xor24:xor2 port map(Sel01,Sel10,T(3)); xor25:xor2 port map(T(3),Sel11,T(4)); and59:and5 port map(T(4),QN(3),Q(2),Q(1),Q(0),Rch); and42:and4 port map(Q(3),QN(2),QN(1),QN(0),Rac); and43:and4 port map(Q(3),QN(2),QN(1),Q(0),Rck); and44:and4 port map(Q(3),QN(2),Q(1),QN(0),Rcp); end vm_structural; not213:not2 port map(S65e,N(12)); not214:not2 port map(S65m,N(13)); not215:not2 port map(CA,N(14)); and61:and6 port map(QN(3),QN(2),QN(1),QN(0),N(0),Rtn,S(0)); and71:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(1)); and72:and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),S65e,N(13),S(2)); and51:and5 port map(QN(3),Q(2),Q(1),QN(0),N(14),S(3)); xor21:xor2 port map(Sel10,N(4),T(0)); and62:and6 port map(QN(3),Q(2),Q(1),Q(0),N(2),T(0),S(4)); or51:or5 port map(S(0),S(1),S(2),S(3),S(4),D(3)); DFF1:DFF port map(D(3),Clk,Q(3),QN(3)); and52:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel11,S(5)); and73:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(6)); and74:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(7)); and75:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(8)); and76:and7 port map(QN(3),Q(2),QN(1),QN(0),N(11),N(12),S65m,S(9)); and53:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(10)); and77:and7 port map(QN(3),Q(2),Q(1),Q(0),Sel01,N(3),N(4),S(11)); or71:or7 port map(S(5),S(6),S(7),S(8),S(9),S(10),S(11),D(2)); DFF2:DFF port map(D(2),Clk,Q(2),QN(2)); and54:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel01,S(12)); and55:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(13)); and78:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),N(6),S50m,S(14)); and79:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),N(9),S60m,S(15)); xor22:xor2 port map(S65e,S65m,T(1)); and64:and6 port map(QN(3),Q(2),QN(1),Q(0),N(11),T(1),S(16)); and56:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(17)); and710:and7 port map(QN(3),Q(2),Q(1),Q(0),N(2),N(3),Sel11,S(18)); or72:or7 port map(S(12),S(13),S(14),S(15),S(16),S(17),S(18),D(1)); DFF3:DFF port map(D(1),Clk,Q(1),QN(1)); and65:and6 port map(QN(3),QN(2),QN(1),QN(0),Mny,N(1),S(19)); and57:and5 port map(QN(3),QN(2),QN(1),Q(0),Sel10,S(20)); and711:and7 port map(QN(3),QN(2),Q(1),QN(0),N(5),S50e,N(7),S(21)); and712:and7 port map(QN(3),QN(2),Q(1),Q(0),N(8),S60e,N(10),S(22)); and58:and5 port map(QN(3),Q(2),Q(1),QN(0),CA,S(23)); xor23:xor2 port map(Sel01,Sel10,T(2)); and66:and6 port map(QN(3),Q(2),Q(1),Q(0),N(4),T(2),S(24)); or61:or6 port map(S(19),S(20),S(21),S(22),S(23),S(24),D(0)); DFF4:DFF port map(D(0),Clk,Q(0),QN(0)); and41:and4 port map(QN(3),Q(2),QN(1),Q(0),Rpp); xor24:xor2 port map(Sel01,Sel10,T(3)); xor25:xor2 port map(T(3),Sel11,T(4)); and59:and5 port map(T(4),QN(3),Q(2),Q(1),Q(0),Rch); and42:and4 port map(Q(3),QN(2),QN(1),QN(0),Rac); and43:and4 port map(Q(3),QN(2),QN(1),Q(0),Rck); and44:and4 port map(Q(3),QN(2),Q(1),QN(0),Rcp); end vm_structural;

Sum Signals Generation Block Nickel Dime Quarter Dollar Pepsi Cookies Chips Sum<50c Sum=50c Sum>50c Sum<60c Sum=60c Sum>60c Sum<65c Sum=65c Sum>65c FIGURE 5

entity sum is port(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; entity sum is port(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit); end sum; architecture sum_bhv of sum is signal sum:integer:=0; --initially sum=0 signal M:bit_vector(3 downto 0); begin M<=M3&M2&M1&M0; process(clk,M) begin if clk='1' and clk'event then s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit); end sum; architecture sum_bhv of sum is signal sum:integer:=0; --initially sum=0 signal M:bit_vector(3 downto 0); begin M<=M3&M2&M1&M0; process(clk,M) begin if clk='1' and clk'event then case M is when "1000" => case M is when "1000" => sum sum sum sum null; sum sum null; end case; end if; end process; process(clk) begin if sel2='1' then if sum 10 then s6 50c elsif sel1='1' then if sum 12 then s3 60c elsif sel0='1' then if sum 13 then s0 65c end if; end process; end sum_bhv; end case; end if; end process; process(clk) begin if sel2='1' then if sum 10 then s6 50c elsif sel1='1' then if sum 12 then s3 60c elsif sel0='1' then if sum 13 then s0 65c end if; end process; end sum_bhv;

entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, entity vm is port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l, S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit); end vm; S65e,S65m,CA,Clk:in bit;Rpp,Rck,Rcp,Rac,Rch: out bit); end vm; architecture vm_bhv of vm is signal s,ns: integer:=0; begin process(s,Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m, architecture vm_bhv of vm is signal s,ns: integer:=0; begin process(s,Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m, S65l,S65e,S65m,CA) begin case s is when 0=> if Mny='0' and Rtn='0' then Rpp if Sel01='1' then Rpp if S50l='1' then Rpp if S60l='1' then Rpp if Mny='0' and Rtn='0' then Rpp if Sel01='1' then Rpp if S50l='1' then Rpp if S60l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S60e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=9;end if; if S60m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if; BEHAVIOR PROGRAM FOR MAIN BLOCK

when 4=> when 4=> if S65l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S65e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=10;end if; if S65m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if; if S65l='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0;end if; if S65e='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=10;end if; if S65m='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=6;end if; when 5=> Rpp Rpp<='1';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=0; when 6=> when 6=> if CA='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=7;end if; if CA='0' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if; if CA='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=7;end if; if CA='0' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='0';ns<=8;end if; when 7=> when 7=> if Sel01='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=5;end if; if Sel10='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=9;end if; if Sel11='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=10;end if; if Sel01='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=5;end if; if Sel10='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=9;end if; if Sel11='1' then Rpp<='0';Rck<='0';Rcp<='0';Rac<='0';Rch<='1';ns<=10;end if; when 8=> Rpp Rpp Rpp null; end case; end process; process(Clk) begin if Clk='1' then s Rpp Rpp Rpp null; end case; end process; process(Clk) begin if Clk='1' then s<=ns; end if; end process; end vm_bhv;

entity newvm is port(Mny,Rtn,Sel01,Sel10,Sel11,nickel,dime,quarter,dollar,CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); end newvm; architecture newvm_structural of newvm is signal sm:bit_vector(8 downto 0); component sum port(clk,M3,M2,M1,M0,sel2,sel1,sel0:in bit; s8,s7,s6,s5,s4,s3,s2,s1,s0:out bit) end component; component vm port(Mny,Rtn,Sel01,Sel10,Sel11,S50l,S50e,S50m,S60l,S60e,S60m,S65l,S65e,S65m, CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); CA,Clk:in bit; Rpp,Rck,Rcp,Rac,Rch: out bit); end component; begin sum1:sum portmap (Clk,nickel,dime,quarter,dollar,Sel01,Sel10,Sel11, sm(8),sm(7), sm(6),sm(5),sm(4),sm(3),sm(2),sm(1),sm(0)); vm1: vm port map (Mny,Rtn,Sel01,Sel10,Sel11,sm(8),sm(7),sm(6), sm(5),sm(4), sm(6),sm(5),sm(4),sm(3),sm(2),sm(1),sm(0)); vm1: vm port map (Mny,Rtn,Sel01,Sel10,Sel11,sm(8),sm(7),sm(6), sm(5),sm(4), sm(3), sm(2),sm(1), sm(0),CA,Clk,Rpp,Rck,Rcp,Rac,Rch); sm(3), sm(2),sm(1), sm(0),CA,Clk,Rpp,Rck,Rcp,Rac,Rch); end newvm_structural; STRUCTURAL PROGRAM FOR VENDING MACHINE CONTROLLER

PLOT 3 STRUCTURAL ARCHITECTURE WAVEFORM FOR RELEASE OF PEPSI

PLOT 4 STRUCTURAL ARCHITECTURE WAVEFORMS FOR RETURNING ALL MONEY