© 2003 Xilinx, Inc. All Rights Reserved System Simulation

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Describe the functionality of SimGen Describe the integration of SimGen within XPS Describe the simulation process Describe what SmartModel™ Libraries are and how to use them

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Outline SimGen Simulation Procedure SmartModel Libraries

System Simulation © 2003 Xilinx, Inc. All Rights Reserved SimGen The Simulation Model Generation tool (SimGen) generates and configures various simulation models for the specified hardware SimGen will generate simulation models by using a Microprocessor Hardware Specification (MHS) file SimGen searches for input files in the following directories located in the project directory – /hdl/ system_name.[vhd|v] peripheral_wrapper.[vhd|v] – /implementation/ (if any of the peripherals are black-box) peripheral_wrapper.ngc system_name.ngc system_name.ncd

System Simulation © 2003 Xilinx, Inc. All Rights Reserved SimGen SimGen produces.[vhd|v] ***.[vhd|v].do _sim.bmm.sdf ** SimGen Generated Directories project_directorysimulation directory * * = behavioral/structural/timing **.sdf in timing simulation ***.[vhd\v] in behavioral or structural simulation

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Memory Initialization To initialize memory in the simulation models created by SimGen, you need: – The compiled executable executable.elf – The simulation hardware model generated by executing SimGen system.vhd or system.v – The BMM file generated by PlatGen /implementation directory Data2MEM system_init.[vhd|v] system.bmm executable.elf system.[vhd|v]

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Memory Initialization The system.bmm file is created by the PlatGen tool and carries block memory related information (see next slide) – Number of block memories – Address range for each set of block memory – Data indexing for each block memory in a set The executable.elf file is generated by the compiler and carries data variables and code The system.vhd file is generated by the SimGen tool and carries a hardware model of the system The Data2MEM program uses the above mentioned files, extracts data code information, and generates a system_init.vhd file that contains block memory initialization content

System Simulation © 2003 Xilinx, Inc. All Rights Reserved System.bmm File ADDRESS_BLOCK plb_bram_if_cntlr_1_bram RAMB16 [0xffffc000:0xffffffff] BUS_BLOCK plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_0 [63:56] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_1 [55:48] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_2 [47:40] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_3 [39:32] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_4 [31:24] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_5 [23:16] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_6 [15:8] ; plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK; ADDRESS_BLOCK plb_bram_if_cntlr_2_bram RAMB16 [0xffff0000:0xffff3fff] BUS_BLOCK plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_0 [63:56] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_1 [55:48] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_2 [47:40] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_3 [39:32] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_4 [31:24] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_5 [23:16] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_6 [15:8] ; plb_bram_if_cntlr_2_bram/plb_bram_if_cntlr_2_bram/ramb16_s9_s9_7 [7:0] ; END_BUS_BLOCK; END_ADDRESS_BLOCK;

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Simulation Libraries: EDK EDK library – Used for behavioral simulation – Contains all of the EDK IP components precompiled for ModelSim  SE and PE – Not available for ModelSim XE – Only VHDL support – Must be compiled for the target simulator – Only the ModelSim simulator is supported Compiling the EDK library by using COMPEDKLIB – compedklib [ -h ] [ -o output-dir-name ] [ -lp repository-dir-name ] [ -X compxlib-output-dir-name ] [ -E compedklib-output-dir-name ]

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Simulation Libraries: XILINX UNISIM library – Used for behavioral simulation and contains default unit delays – Includes all of the Xilinx Unified Library components that are inferred by most popular synthesis tools SIMPRIM library – Used for structural and timing simulation – Includes all of the Xilinx Primitives Library components that are used by Xilinx implementation tools XilinxCoreLib library – Contains pre-optimized modules to take advantage of architectural resources – Library models are used for behavioral simulation – May be used for your own defined IPs Structural and timing simulation models generated by SimGen instantiate the SIMPRIM library components

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Outline SimGen Simulation Procedure SmartModel Libraries

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Integration within XPS Specify simulation parameters by using Options  Project Options – HDL and Simulation tab HDL Simulator Compile Script Simulation Libraries Path – EDK Library – XILINX Library Simulation Models – Hierarchy and Flow tab Submodule ISE Flow Projnav Directory Set up the Project Options 1

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Integration within XPS Generate the simulation models – Generation of simulation models: Tools  Sim Model Generation – Generation of simulation models and simulation initialization: Tools  Hardware Simulation (system model must be top-level) Generate the Simulation Model 2

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Export to ProjNav Copy the files to the ProjNav directory 3 Using Windows Explorer, double-click system.npl 4

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Use within the Project Navigator VHDL – Using Project  New Source  VHDL Test Bench – Using Project  Add Source, add the testbench to the project Verilog – Using Project  New Source  Verilog Test Fixture – Using Project  Add Source, add the testbench to the project Create/Add testbench file 5

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Use within the Project Navigator VHDL – You must copy over the.do simulation file – Testbench.vhd must be added to the.DO file – Testbench.vhd must include a configuration statement to load the RAM initialization strings included in _init.vhd Verilog – You must copy over the.do simulation file – Testbench.v must be added to the.DO file – Testbench.v must include a #include statement to load the RAM initialization strings included in _init.v Copy.DO files to the ProjNav directory Copy.DO files to the ProjNav directory 6

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Outline SimGen Simulation Procedure SmartModel Libraries

System Simulation © 2003 Xilinx, Inc. All Rights Reserved SmartModel Libraries SmartModel  Libraries are compiled simulation models that represent integrated circuits and system buses as black boxes. SmartModel Libraries: – Accept an input stimulus and respond with an appropriate output behavior – Provide improved performance over gate-level models – Protect proprietary designs – Can be used with any simulation tool that supports the SWIFT™ Interface

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Creating SmartModel Libraries SmartModel  Libraries are compiled by using the VMC (Verilog Model Compiler) or the VhMC (VHDL Model Compiler) from Synopsys – Xilinx used VMC to compile a Verilog version of the PowerPC  processor and MGT – You do not need VMC or VhMC to use the Xilinx model Xilinx has compiled each model for a specific OS – Solaris™ Operating System, Windows®, Linux® VMC generates an object file that represents the Verilog file – Internal timing delays are maintained – It is an exact equivalent of the Verilog

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Running a Simulation Using SmartModels The SWIFT™ Interface provides access to SmartModel  Libraries Changes required in the modelsim.ini – Resolution = ps – Comment out the "PathSeparator" = / using “;” – Veriuser = $MODEL_TECH/libswiftpli.dll (SWIFT Interface) – libsm = $MODEL_TECH/libsm.dll – libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll set MODELSIM= \modelsim.ini Instantiate the appropriate MGT or PowerPC  primitive

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Supported Simulators and Platforms Solaris™ Operating System (2.8, 2.9) – MTI's ModelSim  SE simulator (5.6E and newer) – Cadence NC-Verilog  simulator – Cadence Verilog-XL  simulator – Synopsys VCS  simulator Windows® 2000 (SP2) or Windows XP – MTI's ModelSim SE simulator (5.6E and newer) Linux® (7.2) – MTI's ModelSim SE simulator (5.6E and newer)

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Solution Records 14597: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in NC-Verilog, Verilog-XL, and Synopsys VCS? 14019: 6.1i/5.2i/5.1i SmartModel/SWIFT Interface - How do I use the MGT and PPC SmartModels in ModelSim? 14181: Virtex-II Pro - What are the SWIFT Interface, Smart Model, VMC, and VhMC? What of these does Xilinx deliver? 14596: 6.1i SmartModels - What simulators support SmartModel simulation? 14365: Virtex-II Pro PowerPC - What is the difference between Bus Functional Model (BFM) and Smart Model (SWIFT interface) simulation?

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Skills Check

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Review Question Which three items are required to initialize memory in the simulation models created by SimGen?

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Answer Which three items are required to initialize memory in the simulation models created by SimGen? – The compiled executable generated with the appropriate gcc compiler or assembler, from corresponding C or assembly source code – The simulation model generated by executing PlatGen and then SimGen – The BMM file generated by PlatGen

System Simulation © 2003 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Tool documentation – Getting Started with the Embedded Development Kit – Embedded System Tools Guide  Simulation Models Generator Support website – Xilinx Home Page: support.xilinx.com – EDK Home Page: support.xilinx.com/edk