HW (Also, use google scholar to find one or two well cited papers on symmetric models of MOSFET, and quickly study them.) Q: Given a NMOST with VB=VS=0 and V_GS =constant >V_T+0.1V, when V_D is gradually increased from 0 to VDD >> V_GS, how does C_GD vary with V_D? How much total charge goes into or leave the gate terminal? Q: In a scenario similar to last question, examine how C_DB changes as V_D is varied from 0 to VDD=4phi. Let mj =mjsw = 0.5 and phi=phi_0=const. For faster operation, should you use a larger V_D or smaller V_D? Q: Assume level 1 model, hand sketch gm, r_ds and g_ds as V_D changes.

CMOS Device Model Objective –Hand calculations for analog design –Non-idealities and their effects –Efficient and accurate simulation CMOS transistor models –Large signal model –Small signal model –Simulation model –Noise model

Large Signal Model Nonlinear equations for solving dc values of device currents, given voltages Level 1: Shichman-Hodges (V T, K', , and N SUB ) Level 2: with second-order effects (varying channel charge, short-channel, weak inversion, varying surface mobility, etc.) Level 3: Semi-empirical short-channel model Level 4: BSIM models. Based on automatically generated parameters from a process characterization. Good weak-strong inversion transition.

Device is symmetric. Higher voltage side is drain, lower voltage side is source. BSIM5 and PSP models will enforce this symmetry.

Transconductance when V DS is small

Voltage controlled resistor and attenuator

Non-uniform channel potential  non-uniform gate-substrate voltage and non-uniform threshold voltage

Good for V DS <V GS -V TH After that, ID become saturated.

Pro: voltage control of resistivity. Con: nonlinear resistor.

MOST Regions of Operation Cut-off, or non-conducting: v GS <V T –i D =0 Conducting: v GS >=V T –Saturation: v DS > v GS – V T –Triode or linear or ohmic or non-saturation: v DS <= v GS – V T

With channel length modulation

Capacitors Of The Mosfet

C BD and C BS include both the diffusion-bulk junction capacitance as well as the side wall junction capacitance. They are highly nonlinear in bias voltages. C 4 is the capacitance between the channel and the bulk. It is highly nonlinear and depends on the operation of the device. C 4 is not measurable from terminals.

Gate related capacitances

Small signal model

Typically: V DB, V SB are in such a way that there is a reversely biased pn junction. Therefore: g bd ≈ g bs ≈ 0

In saturation: But

Example spice parameter

In non-saturation region

High Frequency Figures of Merit  T AC current source input to G AC short S, D, B to gnd Measure AC drain current output Calculate current gain Find frequency at which current gain = 1. Ignore r s and r d,  C bs, C bd, g ds, g bs, g bd all have zero voltage drop and hence zero current V gs = I in /j  (C gs +C gb +C gd ) ≈ I in /j  (C gs +C gd ) I o = − (g m − j  C gd )V gs ≈ − g m I in /j  (C gs +C gd ) |I o /I in | ≈ g m /  (C gs +C gd )

At  T, current gain =1  T ≈ g m /(C gs +C gd )≈ g m /C gs or

AC current source input to G AC short S, B to gnd Measure AC power into the gate Assume complex conjugate load Compute max power delivered by the transistor Find maximum power gain Find frequency at which power gain = 1. High Frequency Figures of Merit  max

BSIM models Non-uniform charge density Band bending due to non-uniform gate voltage Non-uniform threshold voltage –Non-uniform channel doping, x, y, z –Short channel effects Charge sharing Drain-induced barrier lowering (DIBL) –Narrow channel effects –Temperature dependence Mobility change due to temp, field (x, y) Source, drain, gate, bulk resistances

“Short Channel” Effects V TH decreases for small L –Large offset for diff pairs with small L Mobility reduction: –Velocity saturation –Vertical field (small t ox =6.5nm) –Reduced gm: increases slower than root-I D

Threshold Voltage V TH Strong function of L –Use long channel for V TH matching –But this increases cap and decreases speed Process variations –Run-to-run –How to characterize? –Slow/nominal/fast –Both worst-case & optimistic

Effect of Velocity Saturation Velocity ≈ mobility * field Field reaches maximum E max –(Vgs-Vt)/L reaches E SAT gm become saturated: –gm ≈ ½  n C ox W*E SAT But Cgs still 2/3 WL Cox  T ≈ gm/Cgs = ¾  n E SAT /L No longer ~ 1/L^2

Threshold Reduction When channel is short, effect of Vd extends to S Cause barrier to drop, i.e. Vth to drop Greatly affects sub-threshold current: 26 mV Vth drop  current * e 100~200 mV Vth drop due to Vd not uncommon  100’s or 1000 times current increase Use lower density active near gate but higher density for contacts

Other effects Temperature variation Normal-Field Mobility Degradation Substrate current –Very nonlinear in Vd Drain to source leakage current at Vgs=0 –Big concern for static power Gate leakage currents –Hot electron –Tunneling –Very nonlineary Transit Time Effects

Consequences for Design SPICE (HSPICE or Spectre) –BSIM3, BSIM4 models –Accurate but inappropriate for hand analysis –Verification (& optimization) Design: –Small signal parameter design space: g m, C L (speed, noise) g m /I D, I D (power, output range, speed) A v0 = g m r o (gain) –Device geometries from SPICE (table, graph); –may require iteration (e.g. C GS )

Sweep V1 Measure vgs Intrinsic voltage gain of MOSFET Intrinsic voltage gain = gm/go =  vds/  vgs for constant Id

Intrinsic voltage gain of MOSFET Intrinsic voltage gain = gm/go =  vds/  vgs for constant Id Sweep V1 Measure vgs

Transconductance when V DS is small

Effect of changing V DS for a large V GS

Effect of changing V DS for a given V GS

Effect of changing V DS for various V GS V GS <=V T

Effect of changing V DS for various V GS