Transistor Circuit DC Bias Part 1 ENGI 242
February 2003ENGI 2422 DC Biasing Circuits Fixed-Bias Circuit Emitter-Stabilized Bias Circuit Collector-Emitter Loop Voltage Divider Bias Circuit DC Bias with Voltage Feedback Miscellaneous Bias Circuits
February 2003ENGI 2423 Maximum Power Curve
February 2003ENGI 2424 Fixed-Bias Circuit
February 2003ENGI 2425 DC Equivalent circuit
February 2003ENGI 2426 Base-Emitter (Input) Loop Using Kirchoff’s voltage law: – V CC + I B R B + V BE = 0 Solving for I B :
February 2003ENGI 2427 Collector-Emitter (Output) Loop Since: I C = I B Using Kirchoff’s voltage law: V CE – V CC – I C R C Because: V CE = V C - V E Since V E = 0V, then: V C = V CE Also: V BE = V B - V E with V E = 0V, then: V B = V BE
February 2003ENGI 2428 BJT Saturation Regions When the transistor is operating in the Saturation Region, the transistor is conducting at maximum collector current (based on the resistances in the output circuit, not the spec sheet value) such that:
February 2003ENGI 2429 Determining I csat
February 2003ENGI Determining Icsat for the fixed-bias configuration
February 2003ENGI Load Line Analysis
February 2003ENGI Load Line Analysis The end points of the line are : I Csat and V CE cutoff For load line analysis, use V CE = 0 for I CSAT, and I C = 0 for V CEcutoff I Csat : V CEcutoff : Where I B intersects with the load line we have the Q point Q-point is the particular operating point: Value of R B Sets the value of I B Where I B and Load Line intersect Sets the values of V CE and I C.
February 2003ENGI Circuit values effect Q-point
February 2003ENGI Circuit values effect Q-point (continued)
February 2003ENGI Circuit values effect Q-point (continued)
February 2003ENGI DC Fixed Bias Circuit Example
February 2003ENGI Load-line analysis
February 2003ENGI Fixed-bias load line
February 2003ENGI Movement of Q-point with increasing levels of I B
February 2003ENGI Effect of R C on the load line and Q-point
February 2003ENGI Effect of V CC on the load line and Q-point
February 2003ENGI Example
Emitter Stabilized Bias
February 2003ENGI Emitter-Stabilized Bias Circuit Adding a resistor to the emitter circuit (between the emitter lead and ground) stabilizes the bias circuit
February 2003ENGI Improved Bias Stability The addition of R E to the Emitter improves the stability of a transistor Stability refers to a bias circuit in which the currents and voltages will remain fairly constant for a wide range of temperatures and transistor forward current gain ( ) The temperature surrounding the transistor circuit is not always constant Therefore, the transistor is not a constant value
February 2003ENGI Base-Emitter Loop
February 2003ENGI Equivalent Network
February 2003ENGI Reflected Input impedance of R E
February 2003ENGI Base-Emitter Loop Applying Kirchoffs voltage law:- V CC + I B R B + V BE +I E R E = 0 Since: I E = ( + 1) I B We can write: - V CC + I B R B + V BE + ( + 1) I B R E = 0 Grouping terms and solving for I B : Or we could solve for I E with:
February 2003ENGI Collector-Emitter Loop
February 2003ENGI Collector-Emitter Loop Applying Kirchoff’s voltage law: - V CC + I C R C + V CE + I E R E = 0 Assuming that I E I C and solving for V CE : I C = V CC – V CE – (R E + R C ) Solve for V E : V E = I E R E Solve for V C : V C = V CC - I C R C or V C = V CE + I E R E Solve for V B : V B = V CC - I B R B or V B = V BE + I E R E
February 2003ENGI Transistor Saturation At saturation, V CE is at a minimum We will find the value V CEsat = 0.2V For load line analysis, we use V CE = 0 To solve for I CSAT, use the output KVL equation:
February 2003ENGI Load Line Analysis The load line end points can be calculated: At cutoff: At saturation:
February 2003ENGI Emitter Stabilized Bias Circuit Example
February 2003ENGI Load Line For The Emitter-bias Configuration.