Experiment Electronics UMC 0.18µm radiation hardness studies - Update - Sven Löchner 13 th CBM Collaboration Meeting GSI Darmstadt March 12th, 2009

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 2 Additional Talks & Documents Reference to further talks: EE-Gruppenmeeting ( ) GRISU Statusreport CBM-XYTER Family Planning Workshop ( ) UMC 0.18μm radiation hardness studies IT/EE-Palaver ( ) Untersuchung von Strahlungseffekten in anwendungs- spezifischen integrierten Schaltungen (ASIC) Strahlungseffekte Link:

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 3 Reminder: GRISU project Project objectives: Characterisation of UMC 0.18µm CMOS process concerning the vulnerability against Single Event Effects (SEE), especially Single Event Upsets (SEU) and Single Event Transients (SET) –SEU cross section for different Flip-Flop designs and layouts –Characterisation of the critical charge Q crit respectively the Linear Energy Transfer (LET crit ) –SET sensitivity of the UMC 0.18µm process Single Transistor measurements –Comparison of transistor models by simulation –Total Ionising Dose (TID) Characterisation of the UMC 0.18µm process under irradiation, especially leakage currents, threshold shifts, annealing,...

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 4 GRISU test ASIC Test structures for TID measurements Test structures for SEU measurements Test structures for SET measurements, Q crit Ring oscillator for TID / SEU measurements GRISU chip UMC 0.18µm process 1.5 x 1.5 mm² 64 pads –28 core pads –36 pads

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 5 SEE Building Blocks 3 different building blocks for SEE characterisation: Test structures for SEU measurements –8 different types of flip-flops implemented, e.g. oversized flip- flops, flop-flops with Dual Interlock Cell (DICE) architecture,... Test structures for SET and Q crit measurements –Different inverter chains => Q crit,sim from fC 2 ring oscillator test structure

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 6 X6 cave at GSI Low Energy testing site Installation of a test facility for ASIC irradiation with heavy ions at X6 cave at GSI (in cooperation with bio physics group) Beam monitoring via ionisation chamber Dosimetry setup available Irradiation of DUT in air Easy access Disadvantages of setup: Only one ion source during beam time “Fixed” LET range for ion source

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 7 SEE Tests at GSI SEE test with heavy ions at GSI: X6 experimental site 11.4 MeV/u 7 irradiation tests so far –C-12 (3x) –Ar-40 –Ni-58 –Ru-96 –Xe-132 LET in the range of MeV·cm²/mg (SiO 2 )  Q = fC

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 8 LET testing range Overview of the LET testing range for the applied heavy ions test

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 9 Cross-section (Weibull-Fit) C-12 Ar-40Ni-58Ru-96Xe-132  LET crit = 1.93 MeV cm²/mg  σ sat = 1.48·10 -8 cm²/bit

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 10 Cross-section (DF) LET = 4 MeV cm²/mg

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 11 Dual Interlock Cell (DICE) DICE (Dual Interlock Cell) memory technologies are (more or less) immune against SEU flips. Reference: T. Calin, M. Nicolaidis, R. Velazco Upset Hardened Memory Design for Submicron CMOS Technology IEEE Transactions on Nuclear Science, Vol. 43, No. 6, December 1996

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 12 Layout DICE Latch

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 13 Layout Sense Amp. DICE FF

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 14 SEE Summary Setup of a heavy ion test environment for ASIC irradiation –defined LET value within a range from MeV·cm²/mg (SiO 2 ) Measurement of SEE cross-section for different design cells No SET observed on clock lines  capacitance of clock lines high Not really understood: Higher sensitivity of DICE cells than expected  Heavy ion micro beam scan setup Maybe on a next chip iteration: Triple redundant testing (SEU / SET improvement)

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 15 GRISU 2 – test structures Access to single transistors via core pads –small pad geometry –close to neighbour test pads 16 test structures –NMOS –PMOS –zero-Vt and low-Vt –special transistor layouts (e.g. enclosed, finger) Automatic measurement of transistor characteristics –Output characteristic (U ds – I ds ) –Transfer characteristic (U gs – I ds )

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 16 Total Ionizing Dose (TID) tests TID testing with X-rays –Irradiation facility at Institute for Experimental Nuclear Physics, University of Karlsruhe –60keV X-ray – krad/h 9 GRISU chips tested –Total dose between 800krad and 2500krad(SiO 2 ) –Operating dose rate between 200krad/h and 580krad/h –Two radiation test modes single transistor test structure measurements leakage current, threshold shift, characteristics complete chip measurements transition times, total power consumption

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 17 TID tests – complete chip Power consumption (Pads) –Increase of power consumption by factor of 100 after 1.5Mrad  Leakage current of ESD protection diodes –Good annealing at room temperature  back to pre-radiated value after 6 weeks Power consumption (Core) –Increase by factor of 2 after 1.5 Mrad –Also good annealing at room temperature  back to pre-radiated value after 6 weeks Transition times of minimum size inverter (ring oscillator) –Gets slightly faster up to 250krad –Beyond 250krad noticeable slower  unbalanced NMOS / PMOS ration of inverter –Good annealing at room temperature

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 18 TID tests – single transistors Measurements of the transistor characteristics and calculation of the threshold voltages for different dose levels In total 6 chips are irradiated Total dose up to 2.5Mrad Dose rate between 200krad/h and 580krad/h

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 19 TID tests – single transistors Threshold voltage (Vth) –Almost no further threshold shift after 1Mrad observed –Larger NMOS Vth shift for smaller W –Constant Vth for enclosed transistors (as expected) –More or less no Vth shift for PMOS transistors Leakage current –No significant increase up to 200krad –Scales with gate length L (NMOS) –Zero-Vt: already high leakage current for pre-radiated transistor (≈ 0.5µA) –No increase in leakage for enclosed and PMOS transistors Annealing –Recovery of Vth in the order of 20-40% after 6 weeks –Leakage more or less back to pre-radiated values after 6 weeks

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 20 TID summary UMC process shows good annealing at room temperature (at least at high dose rates) Simulation models slightly differs from measured characteristics (especially between small and large Ugs) Still to be done Second irradiation campaign with low dose rates Long term test with a gamma source

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 21 Thank you

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 22 Additional Transparencies

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 23 Single Event Effects (SEE) SEE: two types of categories Cause of permanent damages (hard errors) Induce of temporary malfunctions (soft errors) Only soft errors are analysed, especially: Single Event Upsets (SEU) Bit flips, e.g. change of states in the digital logic Single Event Transient (SET) Temporary change of the signal level in the circuit, e.g. a glitch

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 24 Linear Energy Transfer (LET) Minimum amount of particle energy induced to a semi- conductor device at which a SEE appears is called LET crit The unit of LET is typical MeV·cm²/mg (related to Si for MOS) d-sensitive depth of penetration  -material density (Si: 2.33g/cm 3 ) Typical values for 0.18µm process technology: d = µm Q crit = fC => LET crit between 1.5 and 12 MeV·cm²/mg

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 25 Charge collection cross-section through an ASIC charge collection under the gate

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 26 GRISU 2 – test structures 4 groups with each 4 single transistor test structures NMOS transistorsW = 0,24 µmL = 1,80 µmW/L = 0,13 W = 2,40 µmL = 0,18 µmW/L = 13,33 W = 0,24 µmL = 0,18 µmW/L = 1,33 W = 2,40 µmL = 1,80 µmW/L = 1,33 Zero-Vt transistorsW = 2,40 µmL = 3,00 µmW/L = 0,80 W = 0,24 µmL = 0,30 µmW/L = 0,80 Low-Vt transistorsW = 0,24 µmL = 0,24 µmW/L = 1,00 W = 2,40 µmL = 2,40 µmW/L = 1,00 Enclosed transistorsW = 2,28 µmL = 0,18 µmW/L = 12,67 W = 6,70 µmL = 1,80 µmW/L = 3,72 Enclosed Zero-VtW = 4,48 µmL = 0,30 µmW/L = 14,93 Finger transistor (10x)W = 10*0,24 µmL = 0,18 µmW/L = 13,33 PMOS transistorsW = 2,40 µmL = 1,80 µmW/L = 1,33 W = 0,24 µmL = 0,18 µmW/L = 1,33 Enclosed PMOS transistorW = 6,70 µmL = 1,80 µmW/L = 3,72 Finger transistor (10x)W = 10*0,24 µmL = 0,18 µmW/L = 13,33

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 27 GRISU 2 – test structures Output characterisation of a minimum size NMOS transistor (0.24 / 0.18) at U gs = 0.6V (left) and U gs = 1.5V (right) Discrepancies between measurements and simulations.

Experiment Electronics March 12th, th CBM Collaboration Meeting - Sven Löchner 28 Vth – simulation vs. measurement Threshold measurement for all test structures. Tendency to higher threshold values for all test structures is visible.