Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course MOS circuits: CMOS circuits, construction

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE n+ SD G V out V in

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The CMOS inverter – recall V DD GND OUT IN n p V DD GND OUT=0 IN=1 V DD GND OUT=1 IN=0 In steady-state only on transistor is "on", the other one is always "off"

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET situations depending on the threshold voltage of the transistors 1. small supply voltage: V DD < V Tn + |V Tp | only one transistor is "on" at a time 2. larger supply voltage V DD > V Tn + |V Tp | when switching over, both transistors are "on" at the same time U IN U V Tn V V Tp V DD V pMOS is "on" 0 0 nMOS is "on" pMOS is V Tp "on" nMOS is "on" Characteristic of the CMOS inverter

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Characteristic of the CMOS inverter ► 1. small supply voltage: V DD < V Tn + |V Tp | a karakterisztika: = DD OUT V U < TnBE VUif << TpDDBETn VVUVifindefinit.... -< TpDDBE VVUif U IN V Tn V DD -V-V Tp V DD V U OUT Indefinit V DD U IN V DD -V-V Tp V DD U OUT V Tn The middle part of the transfer characteristic is very steep, this the specific advantage of CMOS inverters.

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET ► Constructing the characteristic: Characteristic of the CMOS inverter ► 2. large supply voltage: V DD > V Tn + |V Tp | Switching over? - "mutual conduction"

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Design for symmetrical operation: If U IN =U inv logic threshold voltage, both transistors have equal current: U GSp =V DD -U K U GSn =U K The CMOS inverter The inverter logic threshold voltage depends on the ratio of the current constants of the transistors. To have U inv at V DD /2 and V Tn =|V Tp |, then K n =K p has to be set. since hole mobility is times less The logic threshold voltage can be set by the W/L ratios 22 )()( TpinvDDpTninvn VUUKVUK  pn pnTnTpDD inv KK KKVVU U /1 /   

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The CMOS inverter / dynamic char. ► Calculation of the switching times  What do they depend on? the current driving capability of the output the capacitive load on the output ► If the characteristics of the two transistors are exactly complementary (K n =K p and V Tn =|V Tp |), rising and falling times will be equal

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The capacitnces ► Intrinsic capacitances of the driving stage ► Input capacitance of the loading stage (next gate) – extrinsic or fanout capacitances ► wiring (interconnect) capacitance V out1 V in M2M2 M1M1 M4M4 M3M3 V out2 C DB2 C DB1 C GD12 intrinsic MOS transistor capacitances C G4 C G3 extrinsic MOS transistor (fanout) capacitances CwCw wiring (interconnect) capacitance

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The capacitnces ► The intrinsic capacitances:  S-G G-D overlap capacitances  the MOS capacitance of the channel  capacitances of pn junctions ► The wiring capacitance  depends on the interconnect geometry (width, length)  with the advance of manufacturing processes this capacitance tends to increase See later

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The CMOS inverter / dynamic char. ► Calculation of switching times  identical times, integration for the extreme values of the voltage of the load capacitance: V LM – minimal voltage of the load capacitance  If then Can be reduced by increasing the supply voltage or the W/L ratio

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Power consumption of CMOS inv.: ► There is no static consumption since there is no static current ► There is dynamic consumption during switching which consists of 2 parts:  Mutual conduction: During the rise of the input voltage both transistors are "on" V Tn <U IN <V DD -V Tp  Charge pumping: At switching over the output to 1 the C L loading capacitor is charged to the supply voltage through the p transistor, then it is discharged towards the ground through the n transistor. Charge is pumped from VDD to GND.

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Power consumption of CMOS inv.: ► Mutual conduction ("short power"): During a certain period of the rise of the input signal both transistors are "on" if V Tn <U IN <V DD -V Tp this is called mutual conduction charge flowing through:, where t UD is the time while current is flowing, b is a constant depending on the signal shape. b  P ~ f V DD 3

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Power consumption of CMOS inv.: ► Charge pumping: At switching the C L load capacitance is charged to VDD through the p-channel device when the output changes to 1, later, when switching the output to 0, it is discharged towards GND through the n-channel device. P cp =f C L V DD 2 The power consumption due to charge pumping is proportional to the frequency and the square of the supply voltage. ► Total consumption: sum of the two components (if there is mutual conduction), directly proportional to the frequency and the 2 nd and 3 rd power of the supply voltage.

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Components of the consumption of CMOS circuits ► Dynamic components – at every switching event  mutual conduction, charge pumping  proportional to the the event density clock frequency circuit activity ► Further components due to parasitics:  subthreshold currents  leakage currents of pn junctions – nowadays already significant  leakage (tunneling) through the a gate dielectric

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Construction ► Constructing CMOS gates ► Technology (overview of the poly-Si gate process) ► Layout

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET  combination of these: complex gate CMOS gates ► Create an nMOS switching curcuit (pull down network): ► switches: nMOS transistors ► Load: the dual circuit of the nMOS network: pMOS network  series path: NAND function  paralel path: NOR function

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET ► In a CMOS inverter both transistors are actively controlled ► In case of gates there will be a PUN (pull up network: pMOS circuit) and a PDN (pull down network: nMOS circuit). The number of transistors both in PUN and PDN is equal to the number of inputs of the gate  For input combinations where the output is 0, the PDN realizes a short towards GND and the PUN is an open circuit;  if the output function is equal to 1, the PDN will be an open circuit and the PUN realizes a short towards VDD. Circuits with dual topology should be realized from n and p channel transistors ► Gates of transistors receiving the same signal are connected CMOS gates

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET CMOS gates ► NOR gate ► NAND gate For an n input CMOS gate 2n transistors are needed (passive load gates need only n+1 transistors)

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Construction complex CMOS gates ► dual topology (loop  cut, cut  loop) ► dual components: nMOS replaced by pMOS ► transistor gates corresponding to the same signal must be connected ► proper sizing of the W/L ratios (e/h mobility mismatch)

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT DEVICE V out V in n+ SD G

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Metal gate MOS transistor In-depth structure: Layout view: Thin oxide Drain doping Source doping Gate Drain contact Source Problems: metal gate – large V T requires accurate mask alignment

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Poly-Si gate MOS transistor In-depth structure: Layout view: thin oxide Drain doping Source doping Gate Drain contact Source Advantages smaller V T self alignment

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET A poli-Si gate-es nMOS technológia ► Start with: p type substrate (Si wafer) cleaing, grow thick SiO 2 – this is called field oxide

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET expose to UV light through a mask, The poli-Si gate nMOS process ► Create the active zone with photolithography coat with resist, development, removal of exposed resists etching of SiO 2 removal of the resist M1: active zone

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET etch poly-Si, The poli-Si gate nMOS process ► Create the gate structure: pattern poly-Si with photolithography growth of thin oxide deposit poly-Si (resist, exposure,develop) etch thin oxide M2: poly-Si pattern

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The poli-Si gate nMOS process ► S/D doping (implantation) the exide (thin, thick) masks the dopants this way the self-alignment of the gate is assured ► Passivation: deposit PSG

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The poli-Si gate nMOS process ► Open contact windows through PSG photolithography (resist, etching (copy the pattern) M3: contact window pattern expose pattern,develop) cleaning

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET The poli-Si gate nMOS process ► Metallization Deposit Al photolithography, M4: metallization pattern etching, cleaning ► The recepy of the process is given, the in-depth structure is determined by the sequence of the masks ► One needs to specify the shapes on the masks  The set of shapes on subsequent masks is called layout

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Layout of a depletion mode inverter ► Layout == set of 2D shapes on subsequent masks ► Masks are color coded:  active zone: red  poly-Si: green  contact windows:black  metal:blue ► Mask == layout layer S G D S G D Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Layout primitives: simple shapes Gate (mask of poly-Si pattern) Contacts (window opening mask through oxide/PSG) S/D lines (mask of metallization pattern) Active zone (window opening through the oxide)

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET layout of an nMOS transistor: layout primitives on actual layers corresponding to real masks nMOS transistor layout + outline + pinsnMOS transistor macro: outline, pins, scripts: pseudo layers nMOS D S G G Layout macros – from primitives

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Layout macros – from macros and primitives nMOS D S G G pMOSDS G G Gate level layout

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Simplified layout: stick diagram active poly metal contact Vdd Out In GND In Out W/L ratios are given 2/2

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET n+ p-Si substrate n well p+ CMOS structure (inverter)

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Layout macros – from macros and primitives nMOS D S G G pMOSDS G G Gate level layout

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Layout of a CMOS inverter p well n well

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET ► Further masks:  n-well (or p-well, depending on the substrate)  p doping (or n doping, depending on the substrate) ► Multiple metal layer CMOS:  each metallization needs own mask,  conatct windows, vias ► There could be multiple poly-Si layers (analog CMOS) ► Typically: masks ► Certain rules need to be kept for manufacturability: design rules  come from the process, given by Si-foundry CMOS structures

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Details of a CMOS circuit INV NAND3 Layout extraction: checking, real delays 2 metal layers only

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Modern metallization

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Intel 0.25 µm process 5 metal layers Ti/Al - Cu/Ti/TiN Polysilicon dielectric

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Si-compilerek ► Logikai séma vagy magasszintű leírás ► Tranzisztor szintű kapcsolási rajz W/L adatokkal ► Pálcika diagramos layout ► Tényleges layout  automatikus konverzió az egyes leírásmódok között  HARDVERSZINTÉZIS 1.Viselkedési leírásból struktúrális 2.Struktúrális leírás implementációja adott technológiával: technology mapping Most a cél IC megvalósítás alapjait láttuk Lehet FPGA-ra is

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Vezetékek kapacitásai elektromos erővonalak W H t di dielektrikum (SiO 2 ) hordozó C pp = (  di /t di ) WL áramirány dielektromos állandó (SiO 2 => 3.9) L Párhuzamos fegyverzetek: parallel plate capacitance

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET Vezetékek kapacitásai interwire fringe pp C wire = C pp + C fringe + C interwire = (  di /t di )WL + (2  di )/log(t di /H) + (  di /t di )HL párhuzamos lemez szél kapacitás vezetékek közötti H

Budapest University of Technology and Economics Department of Electron Devices CMOS circuits © András Poppe, BME-EET További hatások a vezetékeknél ► Ellenállás ► Elosztott paraméteres RC vonal Diffúziós egyenlet