SRAM Generator -Satya Nalam

2 Motivation SRAM is an integral part of most SoCs Goal: Automate SRAM design process Technology-independence User-independence

3 Overview SRAM Optimizer Schematic script Layout script SRAM schematic SRAM layout leaf cells Design params leaf cells DESIGNER (Cadence SKILL) Project Scope

4 SRAM Architecture SRAM specs Single bank Capacity – 8-32kb Col-mux – 1,2,4,8 #Rows – #Rows and #cols power of 2 Timing block using encounter Schematic/Layout script for tiling each block Wrapper script to generate final SRAM

5 Programmable leaf-cell design E.g. Vias programmed in SKILL for decoder/WL Driver Sized by SRAM optimizier

6 Routing by abutment Routing taking care of internal to leaf cell Leaf-cell 1Leaf-cell 2 Signal between two leaf cells – E.g. WL between WL Driver and Bitcell

7 Example Different column circuitry layouts generated Default, Col-mux=1 Different SA Col-mux=4

8 Status Completed: Full schematic-generation scripts Leaf-cell layout scripts To do: Top-level layout script Usage/Testing: Schematic generation (FreePDK) STT-RAM (Anurag) Schematic + Layout generation (ST 65) BL-leakage cancelling SA (Sudhanshu) Single-ended SA (Joe)

9 Future work Automating leaf-cell layout design Py-cell approach Tie optimizer with SRAM generator E.g. Write optimizer output to config Reduce human intervention Further improve user/technology- independence