Chapter 04 Tutorial Using StateCAD. Objective This tutorial will give you exposure to using StateCAD and VHDL Using HDL Bencher and Modelsim for simulating.

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Presentation transcript:

Chapter 04 Tutorial Using StateCAD

Objective This tutorial will give you exposure to using StateCAD and VHDL Using HDL Bencher and Modelsim for simulating the functional design This tutorial shows you how to create, using StateCAD and VHDL, a simple sequence generator

Sequence Generator State Table Current StateNext StateOutput MABAB DOUT

Sequence Generator State Diagram

Create a New Project

Enter a Name and Location for the Project

Select the Device and Design Flow for the Project

Create a New Source

Select State Diagram and Enter File Name

New Source Information

Next Step

Finish

Create a Blank StateCAD

State Machine Wizard: Draw State Machines

Select the Appearance of the State Machine

Reset the State Machine

Setup Transitions

Placed Template State Diagram

Edit Conditions in the transition arrow State0  State1 Left-Click

Output Wizard

Enter Constraint Value

Completed Transition

Modified State Diagram

Insert a New Transition

Enter Constraint Value

State2  State1

Final State Diagram

Generate HDL

Optimize Outputs for Speed

Result Windows

StateCAD HDL

Create Test Bench (State Bench)

State Bench

Reset

Input CLK

Review Sequence Generator State Table Current StateNext StateOutput MABAB DOUT

Summary Sequence Generator State Table M=0, then State 0  2  1  3  0 …… M=1, then State 0  1  0 ……, State 2  0, and State 3  0.

Check M=0 Then DOUT 0,2,1,3 (State 0,2,1,3)

Check M=1 Then DOUT 0, 1 (State 0,1)

Check M=1 Then State2  State0 and State3  State0

Questions and Answers