Reaction Timer Project Design and implement on the DE2 board a reaction-timer circuit. The circuit is to operate as follows: 1. The circuit is reset by pressing the pushbutton switch KEY0. 2. After an elapsed time, the red light labeled LEDR0 turns on and a four-digit BCD counter starts counting in intervals of milliseconds. The amount of time in seconds from when the circuit is reset until LEDR0 is turned on is set by the output of a pseudo random number generator (PRNG). 3. A person whose reflexes are being tested must press the pushbutton KEY3 as quickly as possible to turn the LED off and freeze the counter in its present state. The count which shows the reaction time will be displayed on the 7-segment displays HEX3-0. Reference: Fundamentals of Digital Logic, section 7.14.3. ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Sequence of Events “w” signal pulse is generated by the Dual OS circuit to light the LED and to trigger the BCD counter. Reaction time (< 1 s) An operator hits KEY0 to reset and trigger the system. Time delay (< 3 s) set by PRNG An user reacts and hits KEY3. The LED goes off and the reaction time is displayed. An operator controls the circuit and the user reacts to the lighting of a LED. Use the reset push button (KEY0) to initialize the system. ECE 3450 M. A. Jupina, VU, 2014

Figure 7.76. A reaction-timer circuit. Stop Key A basic reaction timer circuit described in Brown’s textbook. To put this circuit into practice, additional functionality is required. WARNING: The LEDs on the DE2 are not setup as shown in this schematic. The Stop Key turns off the LED and freezes the counter. KEY3 will be the stop key on the DE2. “w” signal triggers the logic circuit to light the LED and to trigger the BCD counter. ECE 3450 M. A. Jupina, VU, 2014

Figure 7.79. Simulation of the reaction-timer circuit. Example simulation of the proposed system in Brown’s textbook. The simulation of your design will involve more signals to demonstrate the proposed functionality described in these ppt slides. ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Block Diagram Reset Key LED Timing Circuit (Dual OS) “w” signal Reaction Timer Circuit PRNG 7 Segment Displays Delay Value Delayed Pulse Reaction Time Value A block diagram of the reaction timer to be implemented. Stop Key ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Block Diagram Reset Key LED Timing Circuit (Dual OS) “w” signal Reaction Timer Circuit PRNG 7 Segment Displays Delay Value Delayed Pulse Reaction Time Value Stop Key ECE 3450 M. A. Jupina, VU, 2014

Linear Feedback Shift Register A diagram of an eight bit LFSR Linear Feedback Shift Register (LFSR): An n-bit shift register which pseudo-randomly scrolls between 2n-1 values. Once it reaches its final state, it will traverse the sequence exactly as before. Feedback around an LFSR's shift register comes from a selection of points (taps) in the register chain and constitutes XORing these taps to provide tap(s) back into the register. Register bits that do not need an input tap, operate as a standard shift register. It is this feedback that causes the register to loop through repetitive sequences of pseudo-random value. The choice of taps determines how many values there are in a given sequence before the sequence repeats. This functionality can be implemented using the altshift_taps Megafunction found in the Megafunction library in the storage folder. ECE 3450 M. A. Jupina, VU, 2014

Tap Settings The following table shows a minimum number of taps that yield maximal length sequences for LFSRs ranging from 2 to 8 bits. The choice of which taps to use determines how many values are included in a sequence of pseudo-random values before the sequence is repeated. Certain tap settings yield the maximal length sequences of (2n-1). ECE 3450 M. A. Jupina, VU, 2014

The ALTSHIFT_TAPS Megafunction and Its Application in a PRNG Circuit ECE 3450 M. A. Jupina, VU, 2014

An Example of the Simulated Waveforms for the ALTSHIFT_TAPS Megafunction ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Block Diagram Reset Key LED Timing Circuit (Dual OS) “w” signal Reaction Timer Circuit PRNG 7 Segment Displays Delay Value Delayed Pulse Reaction Time Value Stop Key ECE 3450 M. A. Jupina, VU, 2014

Dual OS Circuit to Generate “w signal” (trigger signal to light LED) ? ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Block Diagram Reset Key LED Timing Circuit (Dual OS) “w” signal Reaction Timer Circuit PRNG 7 Segment Displays Delay Value Delayed Pulse Reaction Time Value Stop Key ECE 3450 M. A. Jupina, VU, 2014

Figure 7.77. Code for the two-digit BCD counter in Figure 7.28. LIBRARY ieee ; USE ieee.std_logic_1164.all ; USE ieee.std_logic_unsigned.all ; ENTITY BCDcount IS PORT ( Clock : IN STD_LOGIC ; Clear, E : IN STD_LOGIC ; BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END BCDcount ; ARCHITECTURE Behavior OF BCDcount IS BEGIN PROCESS ( Clock ) IF Clock'EVENT AND Clock = '1' THEN IF Clear = '1' THEN BCD1 <= "0000" ; BCD0 <= "0000" ; ELSIF E = '1' THEN IF BCD0 = "1001" THEN BCD0 <= "0000" ; IF BCD1 = "1001" THEN BCD1 <= "0000"; ELSE BCD1 <= BCD1 + '1' ; END IF ; BCD0 <= BCD0 + '1' ; END IF; END PROCESS; END Behavior ; ECE 3450 M. A. Jupina, VU, 2014

Figure 7.28. A two-digit BCD counter. ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Block Diagram Reset Key LED Timing Circuit (Dual OS) “w” signal Reaction Timer Circuit PRNG 7 Segment Displays Delay Value Delayed Pulse Reaction Time Value Stop Key ECE 3450 M. A. Jupina, VU, 2014

Figure 6.25. A BCD-to-7-segment display code converter. w f b c w 1 d w g 2 e e c w 3 f g d (a) Code converter (b) 7-segment display w w w w a b c d e f g 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (c) Truth table ECE 3450 M. A. Jupina, VU, 2014

Figure 6.47. Code that represents a BCD-to-7-segment decoder. LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY seg7 IS PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ; END seg7 ; ARCHITECTURE Behavior OF seg7 IS BEGIN PROCESS ( bcd ) CASE bcd IS -- abcdefg WHEN "0000" => leds <= "1111110" ; WHEN "0001" => leds <= "0110000" ; WHEN "0010" => leds <= "1101101" ; WHEN "0011" => leds <= "1111001" ; WHEN "0100" => leds <= "0110011" ; WHEN "0101" => leds <= "1011011" ; WHEN "0110" => leds <= "1011111" ; WHEN "0111" => leds <= "1110000" ; WHEN "1000" => leds <= "1111111" ; WHEN "1001" => leds <= "1110011" ; WHEN OTHERS => leds <= "-------" ; END CASE ; END PROCESS ; END Behavior ; ECE 3450 M. A. Jupina, VU, 2014

Hexadecimal to 7-Segment Decoder Outputs Input ETC. ECE 3450 M. A. Jupina, VU, 2014

Clock Divider for DE2 File, Create/Update, Create Symbol Files for Current File will compile the VHDL code and generate a symbol that can be placed in a BDF (block diagram file) in Quartus. When you simulate your design in Quartus, don’t use the Clock Divider block since simulation times will be exceedingly long since everything will be based on a 50 MHz clock signal (20 ns period!!!!!). Instead define the 10 KHz signal, 1 KHz signal, etc. in the vector waveform file. The clock_50MHz input is connected to pin number N2. ECE 3450 M. A. Jupina, VU, 2014

DE2_pin_assignments.csv File To import pin assignments for the DE2 board to your project, go to Assignments, Import Assignments, add the *.csv file, OK ECE 3450 M. A. Jupina, VU, 2014

Settings for Signal Tap II Logic Analyzer @1: EP2C35 (0x020B 40DD) For the above example, the settings are Captured signals: RST, Rec_Play, CLK_10K, we, Start, Cout, Bus, AddSub, Done Trigger: Cout = 0000 Hardware: USB-Blaster Device: EP2C35 Clock: CLK_100K Data Sample Depth: 512 For the Reaction Timer project, the signal tap settings should be basically: Captured signals: Most of the signals that were used in your simulation Trigger: Signal used to turn LED on Clock: CLK_1K Signal (1 KHz signal should give you enough resolution) Data Sample Depth: 1024 ECE 3450 M. A. Jupina, VU, 2014

Example of Signals Displayed in Signal Tap II @1: EP2C35 (0x020B 40DD) ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Pre-Lab Assignment Alter the VHDL code for the two-stage BCD counter in figure 7.77 to create a four-stage BCD counter. Your system will be able to measure a maximum elapsed time of 9.999 s (time resolution is 1 ms). Draw a block diagram of the dual one-shot timing circuit that will be used to create the w trigger signal to turn the LED on. The signal generated by the pushbutton switch KEY0 will be used as an input to this circuit and the output of a Pseudo Random Number Generator will be used to control the time delay in the circuit. Sketch the signal waveforms in your timing circuit. Show all details: switches, pin numbers, clock frequencies used, etc. Draw a block diagram of your Reaction Timer circuit design. Show all details: switches, LED display elements, pin numbers, clock frequencies used, etc. Deliverables: VHDL code, signal waveforms, and two block diagrams. ECE 3450 M. A. Jupina, VU, 2014

Reaction Timer Project Practicum Work Work to be preformed in the Lab: Compile and simulate the four-stage BCD counter. Call this project four_stage_BCD_counter. Compile and simulate the w signal trigger circuit. Call this project w_signal_trigger_circuit. Compile and simulate the Pseudo Random Number Generator circuit. Call this project PRNG_circuit. Compile and simulate the reaction timer circuit. Do not use the clock divider and seven segment decoder blocks in this project. Call this project reaction_timer_simulated. Create a new project, reaction_timer, where the clock divider, seven segment decoders, and pin assignments are added to the project. Compile your design. If the design compiles without errors, then add the Signal Tap II logic analyzer to your project and re-compile. Program the DE2 board and test your design. If your design is not operational, then use the observed signals in the Signal Tap display to debug your design. Record your reaction time. How fast are you? Use the signal tap II logic analyzer to verify the signals of the design. ECE 3450 M. A. Jupina, VU, 2014