WMPI 2006, Austin, Texas © 2006 John C. Koob An Empirical Evaluation of Semiconductor File Memory as a Disk Cache John C. Koob Duncan G. Elliott Bruce.

Slides:



Advertisements
Similar presentations
Fabián E. Bustamante, Spring 2007
Advertisements

1 Parallel Scientific Computing: Algorithms and Tools Lecture #2 APMA 2821A, Spring 2008 Instructors: George Em Karniadakis Leopold Grinberg.
CMSC 611: Advanced Computer Architecture Cache Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material adapted from.
Appendix B. Memory Hierarchy CSCI/ EENG – W01 Computer Architecture 1 Dr. Babak Beheshti Slides based on the PowerPoint Presentations created by.
CMPE 421 Parallel Computer Architecture MEMORY SYSTEM.
Computer Architecture & Organization
Modified from notes by Saeid Nooshabadi COMP3221: Microprocessors and Embedded Systems Lecture 25: Cache - I Lecturer:
Memory Subsystem and Cache Adapted from lectures notes of Dr. Patterson and Dr. Kubiatowicz of UC Berkeley.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Computer Organization Lecture 20 - Memory.
COMP3221 lec33-Cache-I.1 Saeid Nooshabadi COMP 3221 Microprocessors and Embedded Systems Lectures 12: Cache Memory - I
1 COMP 206: Computer Architecture and Implementation Montek Singh Mon, Oct 31, 2005 Topic: Memory Hierarchy Design (HP3 Ch. 5) (Caches, Main Memory and.
331 Lec20.1Fall :332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152.
CIS °The Five Classic Components of a Computer °Today’s Topics: Memory Hierarchy Cache Basics Cache Exercise (Many of this topic’s slides were.
Computer ArchitectureFall 2007 © November 7th, 2007 Majd F. Sakr CS-447– Computer Architecture.
331 Lec20.1Spring :332:331 Computer Architecture and Assembly Language Spring 2005 Week 13 Basics of Cache [Adapted from Dave Patterson’s UCB CS152.
IT Systems Memory EN230-1 Justin Champion C208 –
Virtual Memory Topics Virtual Memory Access Page Table, TLB Programming for locality Memory Mountain Revisited.
4/6/2005 ECE Motivation for Memory Hierarchy What we want from memory  Fast  Large  Cheap There are different kinds of memory technologies  Register.
Memory Hierarchy and Cache Design The following sources are used for preparing these slides: Lecture 14 from the course Computer architecture ECE 201 by.
Systems I Locality and Caching
Computer Architecture Part III-A: Memory. A Quote on Memory “With 1 MB RAM, we had a memory capacity which will NEVER be fully utilized” - Bill Gates.
Chapter 4 ระบบหน่วยความจำ The Memory System
Computing Hardware Starter.
Computers Central Processor Unit. Basic Computer System MAIN MEMORY ALUCNTL..... BUS CONTROLLER Processor I/O moduleInterconnections BUS Memory.
2007 Sept 06SYSC 2001* - Fall SYSC2001-Ch1.ppt1 Computer Architecture & Organization  Instruction set, number of bits used for data representation,
1 Recap (from Previous Lecture). 2 Computer Architecture Computer Architecture involves 3 inter- related components – Instruction set architecture (ISA):
WMPI 2006, Austin, Texas © 2006 John C. Koob An Empirical Evaluation of Semiconductor File Memory as a Disk Cache John C. Koob Duncan G. Elliott Bruce.
9/26: Memory ROM vs. RAM ROM –BIOS RAM –changeable –different kinds & uses inc. VRAM, SRAM –how it works image courtesy of How Computers Work CD.
A Measurement Based Memory Performance Evaluation of High Throughput Servers Garba Isa Yau Department of Computer Engineering King Fahd University of Petroleum.
3 Computing System Fundamentals
What is cache memory?. Cache Cache is faster type of memory than is found in main memory. In other words, it takes less time to access something in cache.
3-May-2006cse cache © DW Johnson and University of Washington1 Cache Memory CSE 410, Spring 2006 Computer Systems
King Fahd University of Petroleum and Minerals King Fahd University of Petroleum and Minerals Computer Engineering Department Computer Engineering Department.
1  1998 Morgan Kaufmann Publishers Recap: Memory Hierarchy of a Modern Computer System By taking advantage of the principle of locality: –Present the.
EEL5708/Bölöni Lec 4.1 Fall 2004 September 10, 2004 Lotzi Bölöni EEL 5708 High Performance Computer Architecture Review: Memory Hierarchy.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
CSE378 Intro to caches1 Memory Hierarchy Memory: hierarchy of components of various speeds and capacities Hierarchy driven by cost and performance In early.
COMP203/NWEN Memory Technologies 0 Plan for Memory Technologies Topic Static RAM (SRAM) Dynamic RAM (DRAM) Memory Hierarchy DRAM Accelerating Techniques.
Introduction: Memory Management 2 Ideally programmers want memory that is large fast non volatile Memory hierarchy small amount of fast, expensive memory.
Caches Hiding Memory Access Times. PC Instruction Memory 4 MUXMUX Registers Sign Ext MUXMUX Sh L 2 Data Memory MUXMUX CONTROLCONTROL ALU CTL INSTRUCTION.
CS2100 Computer Organisation Cache I (AY2015/6) Semester 1.
Topics in Memory System Design 2016/2/5\course\cpeg323-07F\Topic7.ppt1.
Lecture 5: Memory Performance. Types of Memory Registers L1 cache L2 cache L3 cache Main Memory Local Secondary Storage (local disks) Remote Secondary.
Ram is a volatile memory meaning that it can only store its contents as long as its power source is constantly maintained. SDRAM: Dynamic RAM - Inexpensive.
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB ECE232: Hardware Organization and Design Part 14: Memory Hierarchy Chapter 5 (4.
What is it and why do we need it? Chris Ward CS147 10/16/2008.
ECE/CS 552: Cache Concepts © Prof. Mikko Lipasti Lecture notes based in part on slides created by Mark Hill, David Wood, Guri Sohi, John Shen and Jim Smith.
XIP – eXecute In Place Jiyong Park. 2 Contents Flash Memory How to Use Flash Memory Flash Translation Layers (Traditional) JFFS JFFS2 eXecute.
Memory Management memory hierarchy programs exhibit locality of reference - non-uniform reference patterns temporal locality - a program that references.
Test and Characterization of a Variable-Capacity Multilevel DRAM VLSI Test Symposium May 1 - 5, 2005 John Koob, S. Ung, A. Rao, D. Leder, C. Joly, K. Breen,
CMSC 611: Advanced Computer Architecture Memory & Virtual Memory Some material adapted from Mohamed Younis, UMBC CMSC 611 Spr 2003 course slides Some material.
Primary Storage The Triplets – ROM & RAM & Cache.
CMSC 611: Advanced Computer Architecture
COSC3330 Computer Architecture
Memory COMPUTER ARCHITECTURE
CS352H: Computer Systems Architecture
Local secondary storage (local disks)
The Triplets – ROM & RAM & Cache
CSCI206 - Computer Organization & Programming
Chapter 8 Digital Design and Computer Architecture: ARM® Edition
Lecture 14 Virtual Memory and the Alpha Memory Hierarchy
ECE 445 – Computer Organization
Memory Hierarchy Memory: hierarchy of components of various speeds and capacities Hierarchy driven by cost and performance In early days Primary memory.
CMSC 611: Advanced Computer Architecture
Computer System Design Lecture 9
2.C Memory GCSE Computing Langley Park School for Boys.
ECE 463/563 Fall `18 Memory Hierarchies, Cache Memories H&P: Appendix B and Chapter 2 Prof. Eric Rotenberg Fall 2018 ECE 463/563, Microprocessor Architecture,
Take out a piece of paper
Memory Hierarchy Memory: hierarchy of components of various speeds and capacities Hierarchy driven by cost and performance In early days Primary memory.
Cache Memory and Performance
Presentation transcript:

WMPI 2006, Austin, Texas © 2006 John C. Koob An Empirical Evaluation of Semiconductor File Memory as a Disk Cache John C. Koob Duncan G. Elliott Bruce F. Cockburn VLSI Design Lab ECE Department University of Alberta Edmonton, Alberta Canada

WMPI 2006, Austin, Texas Slide 2John C. Koob, University of Alberta Outline  Motivation  Extended Storage  File Memory  Experimental Platform  Cost/Performance Analysis  Conclusions

WMPI 2006, Austin, Texas Slide 3John C. Koob, University of Alberta Motivation Source: Computer Architecture, Hennessy & Patterson, 2003

WMPI 2006, Austin, Texas Slide 4John C. Koob, University of Alberta Access Time Gap Problem  Use Extended Storage  Cheaper per bit than main memory  Faster than disk  Slower than main memory  Potential for power savings  How to fill the access time gap?

WMPI 2006, Austin, Texas Slide 5John C. Koob, University of Alberta Historical Systems  Extended storage first appeared in expensive systems  IBM 3090 mainframe  Main memory: 0.5 GB  Extended storage: 4 GB  Terminology: Expanded Storage Image courtesy of

WMPI 2006, Austin, Texas Slide 6John C. Koob, University of Alberta Historical Systems  Extended storage first appeared in expensive systems  Cray Y-MP supercomputer  Main memory: 1 GB of 15-ns SRAM  Extended storage: 4 GB of 50-ns DRAM  Terminology: Solid State Disk Image courtesy of the Charles Babbage Institute

WMPI 2006, Austin, Texas Slide 7John C. Koob, University of Alberta Recent Research  Compressed caching ( )  Compression can reduce paging costs  Adaptive sizing of compressed page cache  Multi-level main memory (WMPI 2004)  30% of memory must run at DRAM speed  Remaining memory can be slower

WMPI 2006, Austin, Texas Slide 8John C. Koob, University of Alberta Extended Storage Today?  Emerging technology may prompt a return to extended storage  Semiconductor file memory  Up to 5 times slower than DRAM  Cheaper per bit than DRAM  MEMS probe-based storage  5 times faster than disk  10 times more expensive than disk

WMPI 2006, Austin, Texas Slide 9John C. Koob, University of Alberta What is File Memory?  File memory leverages current DRAM technology  DRAM design constraints increase costs per bit  100% of nominal capacity must be functional  Contiguous address space  File memory relaxes DRAM’s design constraints  Bad block marking to improve yield  Address space is not contiguous  Improve density at the expense of performance (e.g. multi-level DRAM or hardware compression)

WMPI 2006, Austin, Texas Slide 10John C. Koob, University of Alberta Feasibility of File Memory  A precedent for file memory exists in the non-volatile memory market  NOR Flash memory  Limited capacity  Moderate reliability  Random-access supported  NAND Flash memory  High capacity  Low reliability  bad block marking  Restricted to sequential access Contiguous Memory Non-Contiguous Memory

WMPI 2006, Austin, Texas Slide 11John C. Koob, University of Alberta Extended Storage Disk Cache  To evaluate file memory as extended storage:  Require an experimental platform  Modify Linux OS kernel  ESDC Design Summary  High memory support  Page cache containment  Configurable performance  CPU caching issues  Performance metrics

WMPI 2006, Austin, Texas Slide 12John C. Koob, University of Alberta Postmark Results using File Memory

WMPI 2006, Austin, Texas Slide 13John C. Koob, University of Alberta Postmark Results Analysis Need 39% more file memory for equivalent performance

WMPI 2006, Austin, Texas Slide 14John C. Koob, University of Alberta Summary of Postmark Results

WMPI 2006, Austin, Texas Slide 15John C. Koob, University of Alberta Conclusions  Use file memory for extended storage  Leverage DRAM cell technology  Relax DRAM design constraints  Use bad block marking  Preliminary evaluation of ESDC  File memory can be up to 4 times slower than DRAM  Performance improved even with no page cache  Ongoing research  Evaluate hierarchies with file memory and page cache

WMPI 2006, Austin, Texas Slide 16John C. Koob, University of Alberta Selected References Bray. Bonnie Castro et al. Adaptive compressed caching. Symp. on Comp. Arch. And High Performance Computing, Nov Ekman and Stenstrom. A case for multi-level main memory. WMPI Hennessy and Patterson. Computer architecture: A quantitative approach. Third Edition, Katcher. PostMark: A new filesystem benchmark. TR3022, Network Appliance, Oct Koob et al. Test and characterization of a variable capacity multilevel DRAM. In Proc. VLSI Test Symp., pp , May Uysal et al. Using MEMS-based storage in disk arrays. FAST 2003, pp

WMPI 2006, Austin, Texas Slide 17John C. Koob, University of Alberta Configurable Performance  How to model different file memory access times?  Use multiple page copies  Gives accurate file memory slowdown ratios  Problem:  Repeated page copies would be cached  Solution:  Disable CPU caches for ESDC – Use IA-32 memory type range registers (MTRRs)

WMPI 2006, Austin, Texas Slide 18John C. Koob, University of Alberta Experimental Setup  Experimental Platform  Processor 2.4 GHz Pentium 4  Memory2 GB DDR SDRAM  Hard disk18-GB Seagate SCSI  Disk buffer4-MB  Experimental Suite  PostMark – benchmark for many small files  Bonnie – file system benchmark  Kernel compilation – Linux kernel build

WMPI 2006, Austin, Texas Slide 19John C. Koob, University of Alberta Postmark Results for Original Hierarchy