STICK DIAGRAM EMT251. Schematic vs Layout In Out V DD GND Inverter circuit.

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Presentation transcript:

STICK DIAGRAM EMT251

Schematic vs Layout In Out V DD GND Inverter circuit

Schematic vs Layout A Out V DD GND B 2-input NAND gate

Stick Diagram A stick diagram is a graphical view of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

Stick Diagram Represents relative positions of transistors Stick diagrams help plan layout quickly  Need not be to scale  Draw with color pencils or dry-erase markers In Out V DD GND Inverter A Out V DD GND B NAND2

Stick Diagram Metal (BLUE) Polysilicion (RED) N-Diffusion (Green) P-Diffusion (Brown) Contact / Via Layers

How to design? C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph / Euler Path

Stick Diagram of C (A + B) X CABABC X V DD GND V DD GND

Consistent Euler Path j V DD X X i GND AB C ABC

Example C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D

LAYOUT DESIGN RULES EMT251

3D View

Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width  scalable design rules: lambda parameter  absolute dimensions (micron rules)

CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

Draw NMOS: 1.Active + Poly 2.Contact_to_active 3.Metal1 above Contact 4.N-Plus Select 5.P-Well 6.P-Well Contact Draw PMOS: 1.Active + Poly 2.Contact_to_active 3.Metal1 above Contact 4.P-Plus Select 5.N-Well 6.N-Well Contact

Layers in 0.35  m CMOS process

Intra-Layer Design Rules Metal2 4 3

Transistor Layout

Vias and Contacts

Select Layer

CMOS Inverter Layout In Out GND V DD (a) Layout