TDTL Architecture with Fast Error Correction Technique ICECS 2010 TDTL Architecture with Fast Error Correction Technique O. Al-Ali, N. Anani, and P. Ponnapalli School of Engineering Manchester Metropolitan University Manchester, UK M. A. Al-Qutayri and S. R. Al-Araji College of Engineering Khalifa University of Science, Technology and Research Sharjah Campus, UAE

Outline Introduction Conventional DTL Conventional TDTL System Conventional Adaptive TDTL Adaptive TDTL Structure Based on Comparison Simulation Results Conclusions and Future work

Introduction Phase Lock Loop Types Analogue Digital

Introduction Digital Phase Lock Loop Types Digital PLLs: Classified as uniform and non-uniform Non-uniform: ZCDPLL: Zero crossing Digital PLL CDTL: Conventional Digital Tanlock Loop Applications Clock recovery, hard drive synchronization, satellite communications

Conventional Digital Tanlock Loop (CDTL)

Digital Tanlock Loop (DTL)cont. Phase Detector Characteristics. where

Digital Tanlock Loop (DTL)cont. Locking Range.

Time Delay Tanlock Loop (TDTL) Block Diagram

Time Delay Tanlock Loop (TDTL) cont. Locking Range. Where , is the steady state phase error

Conventional Adaptive TDTL Block Diagram

Conventional Adaptive TDTL cont. Limitation The feed forward arm is active all the time and hence burdens the loop whether there is a change in the incoming signal Frequency or not. Solution Change the Loop filter only when there is a change in the incoming signal Frequency.

Adaptive TDTL Structure Based on Comparison Block Diagram

Adaptive TDTL Structure Based on Comparison cont. Frequency estimator block diagram.

Adaptive TDTL Structure Based on Comparison cont. Controller block diagram.

Simulation Results FSK Input Signal, (b) (c) FSK Input Signal, (b) FSK Demodulation using Conventional Adaptive DTL, (c) FSK Demodulation using AC-TDTL.

FSK Demodulation using Conventional Adaptive DTL

FSK and Demodulation using AC TDTL

Simulation Results cont. (b) (c) FSK Input Signal, (b) Phase plane of the conventional Adaptive TDTL (c) Phase plane of the proposed system AC-TDTL.

Conclusion and Future works The Adaptive TDTL Structure Based on Comparison compares the frequency of the incoming with that of the DCO signal and acts accordingly without burdening the loop flow. This results in substantial improvement in the acquisition time by more than three times. The proposed architecture will require some additional circuitry compared to the conventional TDTL in order to implement the adaptation mechanism. However, the additional circuit overhead is considered acceptable in order to achieve the fast acquisition performance as demonstrated by the results. Future work will include more extensive evaluation of the loop under different conditions such as noise and high dynamic environment.