Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Computer Organization Lecture 23 RAID Input/output design RS232 serial port example Direct memory access

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering RAID RAID: redundant arrays of inexpensive disks History: Patterson, Gibson, Katz (1987); UC Berkeley Goal: high speed, high reliability, low cost Technique: place data across multiple drives and include redundancy (striping) RAID levels: 0 – 6, define the striping

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Data striping Bit level: each bit of a byte written on a different disk, along with parity Block level: each byte of a file written to a different disk, along with ECC LUN: collection of drives appear as one logical storage unit Multiple, parallel drives: number often a factor of 8, increase bandwidth

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering RAID example: 4 data disks

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Commercial product Features: 7TB, hot swappable (17 drives), 400 MB/s, 7200 rpm drives, $2/GB, RAID 0, 1, 3, 5, 0+1

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering System view of a computer One Agent at-a-time owns the bus ··· Signal 0 Signal n Agent 0 Agent n ··· Bus Signal 1

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Bus timing Clk Breq Bgnt Ack Data Bus Driven ARB ADRDATARESP Address Bus Driven

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering I/O design Memory-mapped –Shared memory and I/O addresses –Some addresses I/O devices, some memory –All memory instructions may operate on an I/O device Separate I/O address space: called ports –Two address spaces: memory and I/O –Unique I/O instructions: in, out

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering General memory design A D Q E R/W A D Q E In 0 E 1 n Address Data R/W Qout (low bits) (upper bits) decoder memory From Lecture 14

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Memory design guide Bus lower addresses to all devices Use upper addresses and decoder for device enables Data bus and other control signals sent to all devices No read-write signal for ROM Bus outputs together because they are tri- stated

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering General I/O design D Q E D Q E In 0 E 1 n Address Data Qout decoder I/O: D flip flops Ctl (Read, Write)

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering I/O design guide Use address, control, and decoder for device reads and writes Data bus sent to all devices Bus outputs together because they are tri- stated

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Example I/O design Bus (simplified) –Address: 8-bit –Data: 8-bit, tri-state (uni-directional) –Control: read, write I/O addresses (Port addresses) –Device 0 = 0xf8 –Device 1 = 0xf9

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Schematic

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Trace Bus floats to 0xff Write to Ports Bus floats to 0xff Read from Ports

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Find decode logic for 4 ports? Port addresses = 0xf8, 0xf9, 0xfa, 0xfb

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Trace Bus floats to 0xff Write to Ports Bus floats to 0xff Read from Ports

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering RS-232 serial port I/O device: USART (universal synchronous asynchronous receiver transmitter) Functionality (similar to shift register) –Transmitter: parallel in, serial out –Receiver: serial in, parallel out –Status Output buffer empty Input buffer full

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering C8251 block diagram parallel in parallel out serial in serial out

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering USART addressing Memory-mapped I/O (MIPS approach) Receiver –Control register: 0xffff 0000 –Data register: 0xffff 0004 Transmitter –Control register: 0xffff 0008 –Data register: 0xffff 000c

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering USART assembly code Definitions for memory-mapped devices

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Receive, transmit subroutines Subroutines to read and write a byte

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Find flowchart for rcvbyte?

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Wait (busy) loop Programming technique –CPU continuously reads control register until non-zero (ready bit set): wait loop –CPU reads/writes data to port Results in poor system utilization: both memory-mapped or separate I/O addresses Known as programmed I/O

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Disadvantages of programmed I/O?

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Direct memory access Objective: avoid the disadvantages of programmed I/O (eliminate busy loop) Technique –CPU writes to special controller (word count and memory address) –CPU tells controller to start data transfers –CPU continues with other computing –CPU responds to interrupt from controller: ISR

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Role of DMA controller Accept initialization data from CPU Access I/O device and drive bus (master) –Input: read I/O device and write data to memory –Output: read memory data and write to I/O device Interrupt CPU when transfer complete

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Programmed I/O Programmed I/O ties up CPU Read I/O Write memory

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering DMA I/O DMA requires little CPU overhead Initialize Multiple transfers

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering DMA time line ISR Interrupt CPU and I/O concurrent in time

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Find decode logic for 4 ports?

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Find flowchart for rcvbyte? Push $ra Get rcv status Char ready? Read and echo char Pop $ra yes no

Fall EE 333 Lillevik 333f06-l23 University of Portland School of Engineering Disadvantages of programmed I/O? 1.CPU cycles result in little computing 2.Memory continuously accessed, possible contention with another CPU 3.One I/O access at a time 4.Bus heavily requested